From 55ae7045135f430db579c4457f49854f34498e67 Mon Sep 17 00:00:00 2001 From: Jason Ekstrand Date: Thu, 27 Aug 2020 17:42:43 -0500 Subject: [PATCH] intel/fs: Add support for vec8 and vec16 ops Reviewed-by: Lionel Landwerlin Part-of: --- src/intel/compiler/brw_fs_nir.cpp | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp index 765f127056a..857ee8ed4b9 100644 --- a/src/intel/compiler/brw_fs_nir.cpp +++ b/src/intel/compiler/brw_fs_nir.cpp @@ -752,6 +752,8 @@ fs_visitor::prepare_alu_destination_and_sources(const fs_builder &bld, case nir_op_vec2: case nir_op_vec3: case nir_op_vec4: + case nir_op_vec8: + case nir_op_vec16: return result; default: break; @@ -1002,14 +1004,16 @@ fs_visitor::nir_emit_alu(const fs_builder &bld, nir_alu_instr *instr, unsigned execution_mode = bld.shader->nir->info.float_controls_execution_mode; - fs_reg op[4]; + fs_reg op[NIR_MAX_VEC_COMPONENTS]; fs_reg result = prepare_alu_destination_and_sources(bld, instr, op, need_dest); switch (instr->op) { case nir_op_mov: case nir_op_vec2: case nir_op_vec3: - case nir_op_vec4: { + case nir_op_vec4: + case nir_op_vec8: + case nir_op_vec16: { fs_reg temp = result; bool need_extra_copy = false; for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++) { -- 2.30.2