From 55c9c653e0a50b0dff0ff18095173829b9fa3a4d Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 4 May 2016 00:59:02 +0200 Subject: [PATCH] adapt to litedram changes --- litex/boards/targets/sim.py | 3 ++- litex/soc/integration/soc_sdram.py | 8 ++++---- 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/litex/boards/targets/sim.py b/litex/boards/targets/sim.py index 39a49111..c04e883a 100755 --- a/litex/boards/targets/sim.py +++ b/litex/boards/targets/sim.py @@ -12,7 +12,8 @@ from litex.soc.integration.builder import * from litex.soc.cores import uart from litex.soc.integration.soc_core import mem_decoder -from litedram.modules import PhySettings, IS42S16160 +from litedram.common import PhySettings +from litedram.modules import IS42S16160 from litedram.phy.model import SDRAMPHYModel from liteeth.phy.model import LiteEthPHYModel diff --git a/litex/soc/integration/soc_sdram.py b/litex/soc/integration/soc_sdram.py index b9c70f71..efc1c810 100644 --- a/litex/soc/integration/soc_sdram.py +++ b/litex/soc/integration/soc_sdram.py @@ -14,7 +14,7 @@ __all__ = ["SoCSDRAM", "soc_sdram_args", "soc_sdram_argdict"] class ControllerInjector(Module, AutoCSR): - def __init__(self, phy, geom_settings, timing_settings, controller_settings): + def __init__(self, phy, geom_settings, timing_settings, **kwargs): self.submodules.dfii = dfii.DFIInjector(geom_settings.addressbits, geom_settings.bankbits, phy.settings.dfi_databits, phy.settings.nphases) self.comb += self.dfii.master.connect(phy.dfi) @@ -22,7 +22,7 @@ class ControllerInjector(Module, AutoCSR): self.submodules.controller = controller = core.LiteDRAMController(phy.settings, geom_settings, timing_settings, - controller_settings) + **kwargs) self.comb += controller.dfi.connect(self.dfii.slave) self.submodules.crossbar = crossbar.LiteDRAMCrossbar(controller.interface, controller.nrowbits) @@ -48,14 +48,14 @@ class SoCSDRAM(SoCCore): raise FinalizeError self._wb_sdram_ifs.append(interface) - def register_sdram(self, phy, geom_settings, timing_settings, controller_settings=None): + def register_sdram(self, phy, geom_settings, timing_settings, **kwargs): assert not self._sdram_phy self._sdram_phy.append(phy) # encapsulate in list to prevent CSR scanning self.submodules.sdram = ControllerInjector(phy, geom_settings, timing_settings, - controller_settings) + **kwargs) dfi_databits_divisor = 1 if phy.settings.memtype == "SDR" else 2 sdram_width = phy.settings.dfi_databits//dfi_databits_divisor -- 2.30.2