From 55d4810f86368bd731402f156512742a9e7489a9 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 9 Jun 2021 21:33:16 +0100 Subject: [PATCH] add some more comments in the mapreduce svp64 examples/unit tests --- src/openpower/decoder/isa/test_caller_svp64_mapreduce.py | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/openpower/decoder/isa/test_caller_svp64_mapreduce.py b/src/openpower/decoder/isa/test_caller_svp64_mapreduce.py index 74c96ba8..04290694 100644 --- a/src/openpower/decoder/isa/test_caller_svp64_mapreduce.py +++ b/src/openpower/decoder/isa/test_caller_svp64_mapreduce.py @@ -47,6 +47,7 @@ class DecoderTestCase(FHDLTestCase): print ("SVSTATE", bin(svstate.spr.asint())) # copy before running, then compute answers expected_regs = deepcopy(initial_regs) + # r1 = r1 + r5 + r6 expected_regs[1] = (initial_regs[1] + initial_regs[5] + initial_regs[6]) # 0x0707 @@ -79,7 +80,9 @@ class DecoderTestCase(FHDLTestCase): with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, svstate=svstate, initial_fprs=fprs) + # answer should be 7.0 * -9.8 * -9.8 * 2.0 = 1344.56 self.assertEqual(sim.fpr(1), SelectableInt(0x4095023d60000000, 64)) + # these should not have been changed self.assertEqual(sim.fpr(2), SelectableInt(0xC02399999999999A, 64)) self.assertEqual(sim.fpr(3), SelectableInt(0xC02399999999999A, 64)) self.assertEqual(sim.fpr(4), SelectableInt(0x4000000000000000, 64)) -- 2.30.2