From 55d936323a06c87737dcb21238dc540bb9368f5d Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 10 Jul 2020 16:28:24 +0100 Subject: [PATCH] add overflow div tests --- src/soc/fu/div/test/test_pipe_caller.py | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/src/soc/fu/div/test/test_pipe_caller.py b/src/soc/fu/div/test/test_pipe_caller.py index dd7d0153..904cf30b 100644 --- a/src/soc/fu/div/test/test_pipe_caller.py +++ b/src/soc/fu/div/test/test_pipe_caller.py @@ -140,6 +140,27 @@ class DIVTestCase(FHDLTestCase): initial_regs[2] = 0xffc868bf4573da0b self.run_tst_program(Program(lst), initial_regs) + def test_divw_by_zero_1(self): + lst = ["divw. 3, 1, 2"] + initial_regs = [0] * 32 + initial_regs[1] = 0x1 + initial_regs[2] = 0x0 + self.run_tst_program(Program(lst), initial_regs) + + def test_divw_overflow2(self): + lst = ["divw. 3, 1, 2"] + initial_regs = [0] * 32 + initial_regs[1] = 0x80000000 + initial_regs[2] = 0xffffffffffffffff # top bits don't seem to matter + self.run_tst_program(Program(lst), initial_regs) + + def test_divw_overflow3(self): + lst = ["divw. 3, 1, 2"] + initial_regs = [0] * 32 + initial_regs[1] = 0x80000000 + initial_regs[2] = 0xffffffff + self.run_tst_program(Program(lst), initial_regs) + def test_rand_divw(self): insns = ["divw", "divw.", "divwo", "divwo."] for i in range(40): -- 2.30.2