From 55e7d3e5b6f062659bad5f6fdc8469ce80f102dd Mon Sep 17 00:00:00 2001 From: Nils Asmussen Date: Fri, 14 Feb 2020 11:45:29 +0100 Subject: [PATCH] arch-riscv: fault on mstatus accesses from lower privilege modes. Change-Id: If2e35445770eaa52f5af6f9ef02fb5e11bef8da4 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25652 Tested-by: kokoro Reviewed-by: Jason Lowe-Power Maintainer: Jason Lowe-Power --- src/arch/riscv/isa/formats/standard.isa | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/src/arch/riscv/isa/formats/standard.isa b/src/arch/riscv/isa/formats/standard.isa index 04121513e..d80c671f2 100644 --- a/src/arch/riscv/isa/formats/standard.isa +++ b/src/arch/riscv/isa/formats/standard.isa @@ -2,6 +2,7 @@ // Copyright (c) 2015 RISC-V Foundation // Copyright (c) 2016-2017 The University of Virginia +// Copyright (c) 2020 Barkhausen Institut // All rights reserved. // // Redistribution and use in source and binary forms, with or without @@ -306,6 +307,18 @@ def template CSRExecute {{ olddata = xc->readMiscReg(MISCREG_FFLAGS) | (xc->readMiscReg(MISCREG_FRM) << FRM_OFFSET); break; + case CSR_MSTATUS: { + auto pm = (PrivilegeMode)xc->readMiscReg(MISCREG_PRV); + if (pm != PrivilegeMode::PRV_M) { + std::string error = csprintf( + "MSTATUS is only accessibly in machine mode\n"); + fault = make_shared(error, machInst); + olddata = 0; + } else { + olddata = xc->readMiscReg(CSRData.at(csr).physIndex); + } + break; + } default: if (CSRData.find(csr) != CSRData.end()) { olddata = xc->readMiscReg(CSRData.at(csr).physIndex); -- 2.30.2