From 560b89a031d2921897228c63302ee857ed2bb179 Mon Sep 17 00:00:00 2001 From: lkcl Date: Thu, 2 Jun 2022 12:00:47 +0100 Subject: [PATCH] --- openpower/sv/svp64_quirks.mdwn | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/openpower/sv/svp64_quirks.mdwn b/openpower/sv/svp64_quirks.mdwn index 2b43e255c..b9dda69cc 100644 --- a/openpower/sv/svp64_quirks.mdwn +++ b/openpower/sv/svp64_quirks.mdwn @@ -62,7 +62,7 @@ getting used to, as it may result in invalid results, but ultimately it is critical to think in terms of the "rules", that everything is Scalar instructions in strict Program Order. -Branch is the one and only place where the Scalar +Branch is the one and only place where the Scalar (non-prefixed) operations differ from the Vector (element) instructions, as explained in a separate section. The @@ -74,6 +74,13 @@ order to support a wide range of parallel boolean condition options which are expected of a Vector / GPU ISA. These save a considerable number of instructions in tight inner loop situations. +Condition Register Fields are 4-bit wide and consequently element-width +overrides make absolutely no sense whatsoever. Therefore the elwidth +override field bits can be used for other purposes when Vectorising +CR Field instructions. Moreover, Rc=1 is completely invalid for +CR operations such as `crand`: Rc=1 is for arithmetic operations, producing +a "co-result" that goes into CR0 or CR1. + # CR weird instructions [[sv/int_cr_predication]] is by far the biggest violator of the SVP64 -- 2.30.2