From 561331ed97f0894abc86c09f2fc5c3d07f571d94 Mon Sep 17 00:00:00 2001 From: Gabriel Somlo Date: Mon, 3 Aug 2020 16:59:39 -0400 Subject: [PATCH] debug: make CI print offending values --- litex/soc/interconnect/axi.py | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/litex/soc/interconnect/axi.py b/litex/soc/interconnect/axi.py index ec25bbae..82d37f35 100644 --- a/litex/soc/interconnect/axi.py +++ b/litex/soc/interconnect/axi.py @@ -496,7 +496,8 @@ class AXILite2Wishbone(Module): def __init__(self, axi_lite, wishbone, base_address=0x00000000): wishbone_adr_shift = log2_int(axi_lite.data_width//8) assert axi_lite.data_width == len(wishbone.dat_r) - assert axi_lite.address_width == len(wishbone.adr) + wishbone_adr_shift + assert axi_lite.address_width == len(wishbone.adr) + wishbone_adr_shift, "axi_addr_w={}; len_wb_adr={}; wb_adr_shift={};".format(axi_lite.address_width, len(wishbone.adr), wishbone_adr_shift) + print("####\n#### axi_addr_w={}; len_wb_adr={}; wb_adr_shift={};\n####".format(axi_lite.address_width, len(wishbone.adr), wishbone_adr_shift)) _data = Signal(axi_lite.data_width) _r_addr = Signal(axi_lite.address_width) @@ -580,7 +581,8 @@ class Wishbone2AXILite(Module): def __init__(self, wishbone, axi_lite, base_address=0x00000000): wishbone_adr_shift = log2_int(axi_lite.data_width//8) assert axi_lite.data_width == len(wishbone.dat_r) - assert axi_lite.address_width == len(wishbone.adr) + wishbone_adr_shift + assert axi_lite.address_width == len(wishbone.adr) + wishbone_adr_shift, "axi_addr_w={}; len_wb_adr={}; wb_adr_shift={};".format(axi_lite.address_width, len(wishbone.adr), wishbone_adr_shift) + print("####\n#### axi_addr_w={}; len_wb_adr={}; wb_adr_shift={};\n####".format(axi_lite.address_width, len(wishbone.adr), wishbone_adr_shift)) _cmd_done = Signal() _data_done = Signal() -- 2.30.2