From 5638268e4d699fe33f71b7f9dc95c50de6e6fa60 Mon Sep 17 00:00:00 2001 From: David Edelsohn Date: Wed, 6 Sep 2000 21:29:14 +0000 Subject: [PATCH] rs6000.md: Correct function unit definitions for cr_logical and mtjmpr. * rs6000.md: Correct function unit definitions for cr_logical and mtjmpr. (sCOND): Additionally fail for sgt, slt, sge, sle if !TARGET_POWER and use portable method for >=0 and floating point >=. Remove associated matchers. From-SVN: r36211 --- gcc/ChangeLog | 8 + gcc/config/rs6000/rs6000.md | 311 +++--------------------------------- 2 files changed, 33 insertions(+), 286 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index ef138d72ea3..5f18e6dec5b 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,11 @@ +2000-09-06 David Edelsohn + + * rs6000.md: Correct function unit definitions for cr_logical and + mtjmpr. + (sCOND): Additionally fail for sgt, slt, sge, sle if !TARGET_POWER + and use portable method for >=0 and floating point >=. Remove + associated matchers. + 2000-09-06 Mark Mitchell * extend.texi: Mark named return value extension as deprecated. diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index cabfd96f512..b3fdd97461c 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -125,7 +125,7 @@ (define_function_unit "iu" 1 0 (and (eq_attr "type" "cr_logical") - (eq_attr "cpu" "rios1,rs64a,mpccore,ppc403,ppc601")) + (eq_attr "cpu" "mpccore,ppc403,ppc601")) 1 1) (define_function_unit "iu" 1 0 @@ -353,7 +353,7 @@ ; fp compare uses fp unit (define_function_unit "fpu" 1 0 (and (eq_attr "type" "fpcompare") - (eq_attr "cpu" "rs64a,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc750")) + (eq_attr "cpu" "rs64a,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750")) 5 1) (define_function_unit "fpu" 1 0 @@ -368,19 +368,18 @@ (define_function_unit "bpu" 1 0 (and (eq_attr "type" "mtjmpr") - (eq_attr "cpu" "rs64a,mpccore,ppc403,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc750")) + (eq_attr "cpu" "mpccore,ppc403,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750")) 4 1) (define_function_unit "bpu" 1 0 (and (eq_attr "type" "cr_logical") - (eq_attr "cpu" "ppc604,ppc620")) + (eq_attr "cpu" "rios1,rios2,ppc604")) 4 1) (define_function_unit "cru" 1 0 (and (eq_attr "type" "cr_logical") - (eq_attr "cpu" "ppc604e")) - 4 1) - + (eq_attr "cpu" "ppc604e,ppc620,ppc630,rs64a")) + 1 1) ; all jumps/branches are executing on the bpu, in 1 cycle, for all machines. (define_function_unit "bpu" 1 0 @@ -9988,8 +9987,9 @@ operands[2] = GEN_INT (INTVAL (operands[1]) >> 32); [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] "" " -{ - if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx) +{ + if (! rs6000_compare_fp_p + && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx)) FAIL; rs6000_emit_sCOND (GT, operands[0]); @@ -10001,26 +10001,37 @@ operands[2] = GEN_INT (INTVAL (operands[1]) >> 32); [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] "" " -{ - if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx) +{ + if (! rs6000_compare_fp_p + && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx)) FAIL; rs6000_emit_sCOND (LT, operands[0]); DONE; }") +;; A >= 0 is best done the portable way for A an integer. (define_expand "sge" [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] "" - "{ rs6000_emit_sCOND (GE, operands[0]); DONE; }") + " +{ + if (! rs6000_compare_fp_p + && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx)) + FAIL; + + rs6000_emit_sCOND (GE, operands[0]); + DONE; +}") ;; A <= 0 is best done the portable way for A an integer. (define_expand "sle" [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] "" " -{ - if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx) +{ + if (! rs6000_compare_fp_p + && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx)) FAIL; rs6000_emit_sCOND (LE, operands[0]); @@ -11462,22 +11473,6 @@ operands[2] = GEN_INT (INTVAL (operands[1]) >> 32); "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3" [(set_attr "length" "12")]) -(define_insn "" - [(set (match_operand:SI 0 "gpc_reg_operand" "=r") - (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") - (const_int 0)))] - "! TARGET_POWER && ! TARGET_POWERPC64" - "nand %0,%1,%1\;{sri|srwi} %0,%0,31" - [(set_attr "length" "8")]) - -(define_insn "" - [(set (match_operand:DI 0 "gpc_reg_operand" "=r") - (ge:DI (match_operand:DI 1 "gpc_reg_operand" "r") - (const_int 0)))] - "TARGET_POWERPC64" - "nand %0,%1,%1\;srdi %0,%0,63" - [(set_attr "length" "8")]) - (define_insn "" [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") (compare:CC @@ -11512,68 +11507,6 @@ operands[2] = GEN_INT (INTVAL (operands[1]) >> 32); (const_int 0)))] "") -(define_insn "" - [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") - (compare:CC - (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") - (const_int 0)) - (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") - (ge:SI (match_dup 1) (const_int 0)))] - "! TARGET_POWER" - "@ - nand %0,%1,%1\;{sri.|srwi.} %0,%0,31 - #" - [(set_attr "type" "compare") - (set_attr "length" "8,12")]) - -(define_split - [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") - (compare:CC - (ge:SI (match_operand:SI 1 "gpc_reg_operand" "") - (const_int 0)) - (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "") - (ge:SI (match_dup 1) (const_int 0)))] - "! TARGET_POWER && reload_completed" - [(set (match_dup 0) - (ge:SI (match_dup 1) (const_int 0))) - (set (match_dup 4) - (compare:CC (match_dup 0) - (const_int 0)))] - "") - -(define_insn "" - [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") - (compare:CC - (ge:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") - (const_int 0)) - (const_int 0))) - (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") - (ge:DI (match_dup 1) (const_int 0)))] - "TARGET_POWERPC64" - "@ - nand %0,%1,%1\;srdi. %0,%0,63 - #" - [(set_attr "type" "compare") - (set_attr "length" "8,12")]) - -(define_split - [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") - (compare:CC - (ge:DI (match_operand:DI 1 "gpc_reg_operand" "") - (const_int 0)) - (const_int 0))) - (set (match_operand:DI 0 "gpc_reg_operand" "") - (ge:DI (match_dup 1) (const_int 0)))] - "TARGET_POWERPC64 && reload_completed" - [(set (match_dup 0) - (ge:DI (match_dup 1) (const_int 0))) - (set (match_dup 4) - (compare:CC (match_dup 0) - (const_int 0)))] - "") - (define_insn "" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") @@ -11660,200 +11593,6 @@ operands[2] = GEN_INT (INTVAL (operands[1]) >> 32); "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0" [(set_attr "length" "12")]) -;; This is (and (neg (ge X (const_int 0))) Y). -;; srawi sign-extends, so these patterrns are 64-bit safe. -(define_insn "" - [(set (match_operand:SI 0 "gpc_reg_operand" "=r") - (and:SI (neg:SI - (lshiftrt:SI - (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) - (const_int 31))) - (match_operand:SI 2 "gpc_reg_operand" "r"))) - (clobber (match_scratch:SI 3 "=&r"))] - "" - "{srai|srawi} %3,%1,31\;andc %0,%2,%3" - [(set_attr "length" "8")]) - -(define_insn "" - [(set (match_operand:DI 0 "gpc_reg_operand" "=r") - (and:DI (neg:DI - (lshiftrt:DI - (not:DI (match_operand:DI 1 "gpc_reg_operand" "r")) - (const_int 63))) - (match_operand:DI 2 "gpc_reg_operand" "r"))) - (clobber (match_scratch:DI 3 "=&r"))] - "TARGET_POWERPC64" - "sradi %3,%1,63\;andc %0,%2,%3" - [(set_attr "length" "8")]) - -(define_insn "" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") - (compare:CC - (and:SI (neg:SI - (lshiftrt:SI - (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) - (const_int 31))) - (match_operand:SI 2 "gpc_reg_operand" "r,r")) - (const_int 0))) - (clobber (match_scratch:SI 3 "=&r,&r"))] - "" - "@ - {srai|srawi} %3,%1,31\;andc. %3,%2,%3 - #" - [(set_attr "type" "compare") - (set_attr "length" "8,12")]) - -(define_split - [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") - (compare:CC - (and:SI (neg:SI - (lshiftrt:SI - (not:SI (match_operand:SI 1 "gpc_reg_operand" "")) - (const_int 31))) - (match_operand:SI 2 "gpc_reg_operand" "")) - (const_int 0))) - (clobber (match_scratch:SI 3 ""))] - "reload_completed" - [(set (match_dup 3) - (and:SI (neg:SI (lshiftrt:SI - (not:SI (match_dup 1)) - (const_int 31))) - (match_dup 2))) - (set (match_dup 0) - (compare:CC (match_dup 3) - (const_int 0)))] - "") - -(define_insn "" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") - (compare:CC - (and:DI (neg:DI - (lshiftrt:DI - (not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) - (const_int 63))) - (match_operand:DI 2 "gpc_reg_operand" "r,r")) - (const_int 0))) - (clobber (match_scratch:DI 3 "=&r,&r"))] - "TARGET_POWERPC64" - "@ - sradi %3,%1,63\;andc. %3,%2,%3 - #" - [(set_attr "type" "compare") - (set_attr "length" "8,12")]) - -(define_split - [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") - (compare:CC - (and:DI (neg:DI - (lshiftrt:DI - (not:DI (match_operand:DI 1 "gpc_reg_operand" "")) - (const_int 63))) - (match_operand:DI 2 "gpc_reg_operand" "")) - (const_int 0))) - (clobber (match_scratch:DI 3 ""))] - "TARGET_POWERPC64 && reload_completed" - [(set (match_dup 3) - (and:DI (neg:DI (lshiftrt:DI - (not:DI (match_dup 1)) - (const_int 63))) - (match_dup 2))) - (set (match_dup 0) - (compare:CC (match_dup 3) - (const_int 0)))] - "") - -(define_insn "" - [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") - (compare:CC - (and:SI (neg:SI - (lshiftrt:SI - (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) - (const_int 31))) - (match_operand:SI 2 "gpc_reg_operand" "r,r")) - (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") - (and:SI (neg:SI (lshiftrt:SI (not:SI (match_dup 1)) - (const_int 31))) - (match_dup 2))) - (clobber (match_scratch:SI 3 "=&r,&r"))] - "" - "@ - {srai|srawi} %3,%1,31\;andc. %0,%2,%3 - #" - [(set_attr "type" "compare") - (set_attr "length" "8,12")]) - -(define_split - [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") - (compare:CC - (and:SI (neg:SI - (lshiftrt:SI - (not:SI (match_operand:SI 1 "gpc_reg_operand" "")) - (const_int 31))) - (match_operand:SI 2 "gpc_reg_operand" "")) - (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "") - (and:SI (neg:SI (lshiftrt:SI (not:SI (match_dup 1)) - (const_int 31))) - (match_dup 2))) - (clobber (match_scratch:SI 3 ""))] - "reload_completed" - [(parallel [(set (match_dup 0) - (and:SI (neg:SI (lshiftrt:SI (not:SI (match_dup 1)) - (const_int 31))) - (match_dup 2))) - (clobber (match_dup 3))]) - (set (match_dup 4) - (compare:CC (match_dup 0) - (const_int 0)))] - "") - -(define_insn "" - [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") - (compare:CC - (and:DI (neg:DI - (lshiftrt:DI - (not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) - (const_int 63))) - (match_operand:DI 2 "gpc_reg_operand" "r,r")) - (const_int 0))) - (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") - (and:DI (neg:DI (lshiftrt:SI (not:DI (match_dup 1)) - (const_int 63))) - (match_dup 2))) - (clobber (match_scratch:SI 3 "=&r,&r"))] - "TARGET_POWERPC64" - "@ - sradi %3,%1,63\;andc. %0,%2,%3 - #" - [(set_attr "type" "compare") - (set_attr "length" "8,12")]) - -(define_split - [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") - (compare:CC - (and:DI (neg:DI - (lshiftrt:DI - (not:DI (match_operand:DI 1 "gpc_reg_operand" "")) - (const_int 63))) - (match_operand:DI 2 "gpc_reg_operand" "")) - (const_int 0))) - (set (match_operand:DI 0 "gpc_reg_operand" "") - (and:DI (neg:DI (lshiftrt:SI (not:DI (match_dup 1)) - (const_int 63))) - (match_dup 2))) - (clobber (match_scratch:SI 3 ""))] - "TARGET_POWERPC64 && reload_completed" - [(parallel [(set (match_dup 0) - (and:DI (neg:DI (lshiftrt:SI (not:DI (match_dup 1)) - (const_int 63))) - (match_dup 2))) - (clobber (match_dup 3))]) - (set (match_dup 4) - (compare:CC (match_dup 0) - (const_int 0)))] - "") - (define_insn "" [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") -- 2.30.2