From 56ae0f0714f2159f34d76d15d4fc4ef1077e708e Mon Sep 17 00:00:00 2001
From: Sebastien Bourdeauducq <sebastien@milkymist.org>
Date: Sat, 23 Feb 2013 19:43:12 +0100
Subject: [PATCH] xilinx_ise: disable SRL extraction on synchronizers

---
 mibuild/xilinx_ise.py | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/mibuild/xilinx_ise.py b/mibuild/xilinx_ise.py
index 4012ca40..a35ccf7d 100644
--- a/mibuild/xilinx_ise.py
+++ b/mibuild/xilinx_ise.py
@@ -2,6 +2,8 @@ import os, struct, subprocess
 from decimal import Decimal
 
 from migen.fhdl.structure import *
+from migen.fhdl.specials import SynthesisDirective
+from migen.genlib.cdc import *
 
 from mibuild.generic_platform import *
 from mibuild.crg import CRG, SimpleCRG
@@ -108,7 +110,23 @@ bitgen -g Binary:Yes -w {build_name}-routed.ncd {build_name}.bit
 	if r != 0:
 		raise OSError("Subprocess failed")
 
+class XilinxMultiRegImpl(MultiRegImpl):
+	def get_fragment(self):
+		disable_srl = set(SynthesisDirective("attribute shreg_extract of {r} is no", r=r)
+			for r in self.regs)
+		return MultiRegImpl.get_fragment(self) + Fragment(specials=disable_srl)
+
+class XilinxMultiReg:
+	@staticmethod
+	def lower(dr):
+		return XilinxMultiRegImpl(dr.i, dr.idomain, dr.o, dr.odomain, dr.n)
+
 class XilinxISEPlatform(GenericPlatform):
+	def get_verilog(self, *args, special_overrides=dict(), **kwargs):
+		so = {MultiReg: XilinxMultiReg}
+		so.update(special_overrides)
+		return GenericPlatform.get_verilog(self, *args, special_overrides=so, **kwargs)
+
 	def build(self, fragment, clock_domains=None, build_dir="build", build_name="top",
 			ise_path="/opt/Xilinx", run=True):
 		tools.mkdir_noerror(build_dir)
-- 
2.30.2