From 56be4ed016c233999b5def110a06a5a40f491523 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 21 Jul 2019 15:53:49 +0100 Subject: [PATCH] add "z" to DivPipeBaseData class so that sign and exponent can be carried (unmodified) through the pipeline --- src/ieee754/div_rem_sqrt_rsqrt/div_pipe.py | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/src/ieee754/div_rem_sqrt_rsqrt/div_pipe.py b/src/ieee754/div_rem_sqrt_rsqrt/div_pipe.py index 3fb20315..24be906f 100644 --- a/src/ieee754/div_rem_sqrt_rsqrt/div_pipe.py +++ b/src/ieee754/div_rem_sqrt_rsqrt/div_pipe.py @@ -5,7 +5,7 @@ from .core import (DivPipeCoreConfig, DivPipeCoreInputData, DivPipeCoreInterstageData, DivPipeCoreOutputData) from ieee754.fpcommon.getop import FPPipeContext -from ieee754.fpcommon.fpbase import FPFormat +from ieee754.fpcommon.fpbase import FPFormat, FPNumBaseRecord class DivPipeConfig: @@ -28,6 +28,9 @@ class DivPipeConfig: class DivPipeBaseData: """ input data base type for ``DivPipe``. + :attribute z: a convenient way to carry the sign and exponent through + the pipeline from when they were computed right at the + start. :attribute out_do_z: FIXME: document :attribute oz: FIXME: document :attribute ctx: FIXME: document @@ -41,6 +44,7 @@ class DivPipeBaseData: """ Create a ``DivPipeBaseData`` instance. """ self.config = config width = config.pspec.width + self.z = FPNumBaseRecord(width, False) # s and e carried: m ignored self.out_do_z = Signal(reset_less=True) self.oz = Signal(width, reset_less=True) @@ -50,13 +54,14 @@ class DivPipeBaseData: def __iter__(self): """ Get member signals. """ + yield from self.z yield self.out_do_z yield self.oz yield from self.ctx def eq(self, rhs): """ Assign member signals. """ - return [self.out_do_z.eq(i.out_do_z), self.oz.eq(i.oz), + return [self.z.eq(rhz.z, self.out_do_z.eq(i.out_do_z), self.oz.eq(i.oz), self.ctx.eq(i.ctx)] -- 2.30.2