From 56c9ef5f2fa5787ddd7b2c83804a46554fa1ffc9 Mon Sep 17 00:00:00 2001 From: Kyrylo Tkachov Date: Thu, 28 Apr 2016 12:24:47 +0000 Subject: [PATCH] [AArch64] Define WORD_REGISTER_OPERATIONS to zero and comment why * config/aarch64/aarch64.h (WORD_REGISTER_OPERATIONS): Define to 0 and explain why in a comment. From-SVN: r235563 --- gcc/ChangeLog | 5 +++++ gcc/config/aarch64/aarch64.h | 7 ++++++- 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 40258635363..0284c895ae6 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2015-04-28 Kyrylo Tkachov + + * config/aarch64/aarch64.h (WORD_REGISTER_OPERATIONS): Define to 0 + and explain why in a comment. + 2016-04-28 Claudiu Zissulescu * config/arc/arc.md (cpu_facility): Add fpx variant. diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h index 15d7e4019ad..4135da1becd 100644 --- a/gcc/config/aarch64/aarch64.h +++ b/gcc/config/aarch64/aarch64.h @@ -722,7 +722,12 @@ do { \ #define USE_STORE_PRE_INCREMENT(MODE) 0 #define USE_STORE_PRE_DECREMENT(MODE) 0 -/* ?? #define WORD_REGISTER_OPERATIONS */ +/* WORD_REGISTER_OPERATIONS does not hold for AArch64. + The assigned word_mode is DImode but operations narrower than SImode + behave as 32-bit operations if using the W-form of the registers rather + than as word_mode (64-bit) operations as WORD_REGISTER_OPERATIONS + expects. */ +#define WORD_REGISTER_OPERATIONS 0 /* Define if loading from memory in MODE, an integral mode narrower than BITS_PER_WORD will either zero-extend or sign-extend. The value of this -- 2.30.2