From 56d48227195139f9b85c9f868a192c116266dac4 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 10 Jun 2015 07:24:26 +0200 Subject: [PATCH] Renamed "aig" to "aigmap" --- passes/techmap/Makefile.inc | 2 +- passes/techmap/{aig.cc => aigmap.cc} | 10 +++++----- passes/tests/test_cell.cc | 8 ++++---- 3 files changed, 10 insertions(+), 10 deletions(-) rename passes/techmap/{aig.cc => aigmap.cc} (94%) diff --git a/passes/techmap/Makefile.inc b/passes/techmap/Makefile.inc index 3cbee5b85..e39d5c5c2 100644 --- a/passes/techmap/Makefile.inc +++ b/passes/techmap/Makefile.inc @@ -18,7 +18,7 @@ OBJS += passes/techmap/dff2dffe.o OBJS += passes/techmap/dffinit.o OBJS += passes/techmap/pmuxtree.o OBJS += passes/techmap/muxcover.o -OBJS += passes/techmap/aig.o +OBJS += passes/techmap/aigmap.o endif GENFILES += passes/techmap/techmap.inc diff --git a/passes/techmap/aig.cc b/passes/techmap/aigmap.cc similarity index 94% rename from passes/techmap/aig.cc rename to passes/techmap/aigmap.cc index 3bd078537..9f552e3e5 100644 --- a/passes/techmap/aig.cc +++ b/passes/techmap/aigmap.cc @@ -23,12 +23,12 @@ USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN -struct AigPass : public Pass { - AigPass() : Pass("aig", "convert logic to and-inverter circuit") { } +struct AigmapPass : public Pass { + AigmapPass() : Pass("aigmap", "map logic to and-inverter-graph circuit") { } virtual void help() { log("\n"); - log(" aig [options] [selection]\n"); + log(" aigmap [options] [selection]\n"); log("\n"); log("Replace all logic cells with circuits made of only $_AND_ and\n"); log("$_NOT_ cells.\n"); @@ -41,7 +41,7 @@ struct AigPass : public Pass { { bool nand_mode = false; - log_header("Executing AIG pass (converting logic to AIG).\n"); + log_header("Executing AIGMAP pass (map logic to AIG).\n"); size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) @@ -144,6 +144,6 @@ struct AigPass : public Pass { module->remove(cell); } } -} AigPass; +} AigmapPass; PRIVATE_NAMESPACE_END diff --git a/passes/tests/test_cell.cc b/passes/tests/test_cell.cc index 9a7934f55..bd3749b71 100644 --- a/passes/tests/test_cell.cc +++ b/passes/tests/test_cell.cc @@ -536,8 +536,8 @@ struct TestCellPass : public Pass { log(" -simlib\n"); log(" use \"techmap -map +/simlib.v -max_iter 2 -autoproc\"\n"); log("\n"); - log(" -aig\n"); - log(" instead of calling \"techmap\", call \"aig\"\n"); + log(" -aigmap\n"); + log(" instead of calling \"techmap\", call \"aigmap\"\n"); log("\n"); log(" -muxdiv\n"); log(" when creating test benches with dividers, create an additional mux\n"); @@ -603,8 +603,8 @@ struct TestCellPass : public Pass { techmap_cmd = "techmap -map +/simlib.v -max_iter 2 -autoproc"; continue; } - if (args[argidx] == "-aig") { - techmap_cmd = "aig"; + if (args[argidx] == "-aigmap") { + techmap_cmd = "aigmap"; continue; } if (args[argidx] == "-muxdiv") { -- 2.30.2