From 56e15bf31c0a88d220d5907a533d59ca6341d96a Mon Sep 17 00:00:00 2001 From: Jason Ekstrand Date: Thu, 5 Mar 2020 11:46:51 -0600 Subject: [PATCH] iris: Use ISL_AUX_USAGE_STC_CCS for stencil CCS Reviewed-by: Nanley Chery Part-of: --- src/gallium/drivers/iris/iris_blit.c | 4 ++++ src/gallium/drivers/iris/iris_resolve.c | 3 ++- src/gallium/drivers/iris/iris_resource.c | 14 +++++++++++--- 3 files changed, 17 insertions(+), 4 deletions(-) diff --git a/src/gallium/drivers/iris/iris_blit.c b/src/gallium/drivers/iris/iris_blit.c index 43382f91954..a7aca922e80 100644 --- a/src/gallium/drivers/iris/iris_blit.c +++ b/src/gallium/drivers/iris/iris_blit.c @@ -597,6 +597,10 @@ get_copy_region_aux_settings(struct iris_context *ice, */ *out_clear_supported = devinfo->gen >= 9; break; + case ISL_AUX_USAGE_STC_CCS: + *out_aux_usage = res->aux.usage; + *out_clear_supported = false; + break; default: *out_aux_usage = ISL_AUX_USAGE_NONE; *out_clear_supported = false; diff --git a/src/gallium/drivers/iris/iris_resolve.c b/src/gallium/drivers/iris/iris_resolve.c index fdb45a37c71..2208226e607 100644 --- a/src/gallium/drivers/iris/iris_resolve.c +++ b/src/gallium/drivers/iris/iris_resolve.c @@ -499,7 +499,7 @@ iris_resolve_color(struct iris_context *ice, /* On Gen >= 12, Stencil buffer with lossless compression needs to be * resolve with WM_HZ_OP packet. */ - if (isl_surf_usage_is_stencil(res->surf.usage)) { + if (res->aux.usage == ISL_AUX_USAGE_STC_CCS) { blorp_hiz_stencil_op(&blorp_batch, &surf, level, layer, 1, resolve_op); } else { @@ -962,6 +962,7 @@ iris_resource_texture_aux_usage(struct iris_context *ice, case ISL_AUX_USAGE_MCS: case ISL_AUX_USAGE_MCS_CCS: + case ISL_AUX_USAGE_STC_CCS: return res->aux.usage; case ISL_AUX_USAGE_CCS_D: diff --git a/src/gallium/drivers/iris/iris_resource.c b/src/gallium/drivers/iris/iris_resource.c index 8142c42f3dc..cec772c7178 100644 --- a/src/gallium/drivers/iris/iris_resource.c +++ b/src/gallium/drivers/iris/iris_resource.c @@ -492,6 +492,8 @@ iris_resource_configure_aux(struct iris_screen *screen, } else { res->aux.possible_usages |= 1 << ISL_AUX_USAGE_HIZ_CCS; } + } else if (has_ccs && isl_surf_usage_is_stencil(res->surf.usage)) { + res->aux.possible_usages |= 1 << ISL_AUX_USAGE_STC_CCS; } else if (has_ccs) { if (want_ccs_e_for_format(devinfo, res->surf.format)) res->aux.possible_usages |= 1 << ISL_AUX_USAGE_CCS_E; @@ -542,6 +544,7 @@ iris_resource_configure_aux(struct iris_screen *screen, break; case ISL_AUX_USAGE_CCS_D: case ISL_AUX_USAGE_CCS_E: + case ISL_AUX_USAGE_STC_CCS: /* When CCS_E is used, we need to ensure that the CCS starts off in * a valid state. From the Sky Lake PRM, "MCS Buffer for Render * Target(s)": @@ -555,11 +558,13 @@ iris_resource_configure_aux(struct iris_screen *screen, * For CCS_D, do the same thing. On Gen9+, this avoids having any * undefined bits in the aux buffer. */ - if (imported) + if (imported) { + assert(res->aux.usage != ISL_AUX_USAGE_STC_CCS); initial_state = isl_drm_modifier_get_default_aux_state(res->mod_info->modifier); - else + } else { initial_state = ISL_AUX_STATE_PASS_THROUGH; + } *alloc_flags |= BO_ALLOC_ZEROED; break; case ISL_AUX_USAGE_MC: @@ -1803,13 +1808,16 @@ iris_transfer_map(struct pipe_context *ctx, if (resource->target != PIPE_BUFFER) { bool need_hiz_resolve = iris_resource_level_has_hiz(res, level); + bool need_stencil_resolve = res->aux.usage == ISL_AUX_USAGE_STC_CCS; need_color_resolve = (res->aux.usage == ISL_AUX_USAGE_CCS_D || res->aux.usage == ISL_AUX_USAGE_CCS_E) && iris_has_color_unresolved(res, level, 1, box->z, box->depth); - need_resolve = need_color_resolve || need_hiz_resolve; + need_resolve = need_color_resolve || + need_hiz_resolve || + need_stencil_resolve; } bool map_would_stall = false; -- 2.30.2