From 56e8cbd65cc4c37f29c9816d73fba59fad39db9c Mon Sep 17 00:00:00 2001 From: Jacob Lifshay Date: Thu, 22 Sep 2022 20:36:39 -0700 Subject: [PATCH] link to pseudo-code in openpower-isa.git --- openpower/prefix_codes.mdwn | 37 +------------------------------------ 1 file changed, 1 insertion(+), 36 deletions(-) diff --git a/openpower/prefix_codes.mdwn b/openpower/prefix_codes.mdwn index f09760179..9bd0e0eb9 100644 --- a/openpower/prefix_codes.mdwn +++ b/openpower/prefix_codes.mdwn @@ -50,42 +50,7 @@ and so on for t[16..] Decoding a code word works by walking on the tree from the root to the children, matching each passed 0 or 1 to the next read input bit in RB in LSB to MSB order. When `t[i]` is set, then a valid code word was read and `i` is written to the next byte of output in RT in LSB to MSB order. When no set `t[i]` is encountered, and there are still input bits left, then the code word is >6-bits, so SO/OV/OV32 are set, and decoding stops. -# [DRAFT] Prefix-code decode - -sorta-VA-Form - -* pcdec RT,RA,RB,RC,imm - -Pseudo-code: - - tree[0:63] <- (RA) - in_bits[0:63] <- (RB) - in_pos <- (RC) - decoded_in_pos <- in_pos - output <- [0] * 64 - out_byte <- 0 - decoded[0:7] <- 1 - overflow <- 0 - do while in_pos =u 64 then - overflow <- 1 - break - if tree[63 - decoded] then - decoded_in_pos <- in_pos - output[56 - 8 * out_byte:63 - 8 * out_byte] <- decoded - decoded <- 1 - out_byte <- out_byte + 1 - if imm | (out_byte >=u 8) then - break - RT <- output - RS <- decoded_in_pos - -Special Registers Altered: - - SO OV OV32 +[[!inline pages="openpower/isa/prefix_codes" quick="yes" raw="yes" ]] # [DRAFT] Prefix-code encode -- 2.30.2