From 56f2a77a4149e637d8524780bed121979e7d134e Mon Sep 17 00:00:00 2001 From: =?utf8?q?Marek=20Ol=C5=A1=C3=A1k?= Date: Thu, 11 Jun 2020 04:30:04 -0400 Subject: [PATCH] ac/surface: enable DCC for the first level in the mip tail on gfx10 Acked-by: Pierre-Eric Pelloux-Prayer Part-of: --- src/amd/common/ac_surface.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c index be55e6deaaa..206cdd26dbe 100644 --- a/src/amd/common/ac_surface.c +++ b/src/amd/common/ac_surface.c @@ -1481,7 +1481,16 @@ static int gfx9_compute_miptree(struct ac_addrlib *addrlib, */ for (unsigned i = 0; i < in->numMipLevels; i++) { if (meta_mip_info[i].inMiptail) { - surf->num_dcc_levels = i; + /* GFX10 can only compress the first level + * in the mip tail. + * + * TODO: Try to do the same thing for gfx9 + * if there are no regressions. + */ + if (info->chip_class >= GFX10) + surf->num_dcc_levels = i + 1; + else + surf->num_dcc_levels = i; break; } } -- 2.30.2