From 56f46aa0f9688c87ce9ebd7658e19b884b018b6b Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Tue, 6 Dec 2016 17:04:14 -0800 Subject: [PATCH] avoid non-standard predefined macros --- benchmarks/common/crt.S | 4 ++-- debug/programs/entry.S | 2 +- debug/programs/mprv.S | 4 ++-- debug/programs/regs.S | 2 +- debug/programs/trigger.S | 4 ++-- env | 2 +- isa/rv64mi/breakpoint.S | 4 ++-- isa/rv64mi/ma_addr.S | 4 ++-- isa/rv64mi/mcsr.S | 2 +- isa/rv64uc/rvc.S | 12 ++++++------ isa/rv64uf/fcvt.S | 2 +- isa/rv64uf/fcvt_w.S | 8 ++++---- isa/rv64ui/sll.S | 2 +- isa/rv64ui/slli.S | 2 +- isa/rv64ui/srl.S | 2 +- isa/rv64ui/srli.S | 2 +- 16 files changed, 29 insertions(+), 29 deletions(-) diff --git a/benchmarks/common/crt.S b/benchmarks/common/crt.S index ea07099..de1d728 100644 --- a/benchmarks/common/crt.S +++ b/benchmarks/common/crt.S @@ -2,7 +2,7 @@ #include "encoding.h" -#ifdef __riscv64 +#if __riscv_xlen == 64 # define LREG ld # define SREG sd # define REGBYTES 8 @@ -56,7 +56,7 @@ _start: # make sure XLEN agrees with compilation choice csrr t0, misa -#ifdef __riscv64 +#if __riscv_xlen == 64 bltz t0, 1f #else bgez t0, 1f diff --git a/debug/programs/entry.S b/debug/programs/entry.S index 6dc694f..a2c7304 100755 --- a/debug/programs/entry.S +++ b/debug/programs/entry.S @@ -5,7 +5,7 @@ #define STACK_SIZE 512 -#ifdef __riscv64 +#if __riscv_xlen == 64 # define LREG ld # define SREG sd # define REGBYTES 8 diff --git a/debug/programs/mprv.S b/debug/programs/mprv.S index 115ccb5..5e21607 100644 --- a/debug/programs/mprv.S +++ b/debug/programs/mprv.S @@ -12,7 +12,7 @@ main: # update mstatus csrr t1, CSR_MSTATUS -#ifdef __riscv32 +#if __riscv_xlen == 32 li t0, (MSTATUS_MPRV | (VM_SV32 << 24)) #else li t0, (MSTATUS_MPRV | (VM_SV39 << 24)) @@ -38,7 +38,7 @@ data: .balign 0x1000 page_table: -#ifdef __riscv32 +#if __riscv_xlen == 32 .word ((0x80000000 >> 2) | PTE_V | PTE_R | PTE_W | PTE_X | PTE_G | PTE_U) #else .word ((0x80000000 >> 2) | PTE_V | PTE_R | PTE_W | PTE_X | PTE_G | PTE_U) diff --git a/debug/programs/regs.S b/debug/programs/regs.S index 2cacd4f..5c4f462 100644 --- a/debug/programs/regs.S +++ b/debug/programs/regs.S @@ -1,4 +1,4 @@ -#ifdef __riscv64 +#if __riscv_xlen == 64 # define LREG ld # define SREG sd # define REGBYTES 8 diff --git a/debug/programs/trigger.S b/debug/programs/trigger.S index 1efafc7..48cd68b 100644 --- a/debug/programs/trigger.S +++ b/debug/programs/trigger.S @@ -1,6 +1,6 @@ #include "../../env/encoding.h" -#ifdef __riscv64 +#if __riscv_xlen == 64 # define LREG ld # define SREG sd # define REGBYTES 8 @@ -12,7 +12,7 @@ #undef MCONTROL_TYPE #undef MCONTROL_DMODE -#ifdef __riscv64 +#if __riscv_xlen == 64 # define MCONTROL_TYPE (0xf<<(64-4)) # define MCONTROL_DMODE (1<<(64-5)) #else diff --git a/env b/env index ce70afb..9e219c9 160000 --- a/env +++ b/env @@ -1 +1 @@ -Subproject commit ce70afbf50a203be04bc326326cfa75831fe7f5d +Subproject commit 9e219c9ca70459bfda9067d637bb8bf52c5f0326 diff --git a/isa/rv64mi/breakpoint.S b/isa/rv64mi/breakpoint.S index b318c30..ba683cc 100644 --- a/isa/rv64mi/breakpoint.S +++ b/isa/rv64mi/breakpoint.S @@ -23,7 +23,7 @@ RVTEST_CODE_BEGIN # Make sure there's a breakpoint there. csrr a0, tdata1 - srli a0, a0, _RISCV_SZLONG-4 + srli a0, a0, __riscv_xlen - 4 li a1, 2 bne a0, a1, pass @@ -90,7 +90,7 @@ RVTEST_CODE_BEGIN # Make sure there's a breakpoint there. csrr a0, tdata1 - srli a0, a0, _RISCV_SZLONG-4 + srli a0, a0, __riscv_xlen - 4 li a1, 2 bne a0, a1, pass diff --git a/isa/rv64mi/ma_addr.S b/isa/rv64mi/ma_addr.S index 6e7be94..be3572f 100644 --- a/isa/rv64mi/ma_addr.S +++ b/isa/rv64mi/ma_addr.S @@ -31,7 +31,7 @@ RVTEST_CODE_BEGIN MISALIGNED_LDST_TEST(5, lw, s0, 2) MISALIGNED_LDST_TEST(6, lw, s0, 3) -#ifdef __riscv64 +#if __riscv_xlen == 64 MISALIGNED_LDST_TEST(7, lwu, s0, 1) MISALIGNED_LDST_TEST(8, lwu, s0, 2) MISALIGNED_LDST_TEST(9, lwu, s0, 3) @@ -53,7 +53,7 @@ RVTEST_CODE_BEGIN MISALIGNED_LDST_TEST(24, sw, s0, 2) MISALIGNED_LDST_TEST(25, sw, s0, 3) -#ifdef __riscv64 +#if __riscv_xlen == 64 MISALIGNED_LDST_TEST(26, sd, s0, 1) MISALIGNED_LDST_TEST(27, sd, s0, 2) MISALIGNED_LDST_TEST(28, sd, s0, 3) diff --git a/isa/rv64mi/mcsr.S b/isa/rv64mi/mcsr.S index b66611c..e0256e7 100644 --- a/isa/rv64mi/mcsr.S +++ b/isa/rv64mi/mcsr.S @@ -14,7 +14,7 @@ RVTEST_RV64M RVTEST_CODE_BEGIN # Check that mcpuid reports the correct XLEN -#ifdef __riscv64 +#if __riscv_xlen == 64 TEST_CASE(2, a0, 0x2, csrr a0, misa; srl a0, a0, 62) #else TEST_CASE(2, a0, 0x1, csrr a0, misa; srl a0, a0, 30) diff --git a/isa/rv64uc/rvc.S b/isa/rv64uc/rvc.S index 4a91783..2b8acd2 100644 --- a/isa/rv64uc/rvc.S +++ b/isa/rv64uc/rvc.S @@ -40,18 +40,18 @@ RVTEST_CODE_BEGIN la a1, data RVC_TEST_CASE (6, a2, 0xfffffffffedcba99, c.lw a0, 4(a1); addi a0, a0, 1; c.sw a0, 4(a1); c.lw a2, 4(a1)) -#ifdef __riscv64 +#if __riscv_xlen == 64 RVC_TEST_CASE (7, a2, 0xfedcba9976543211, c.ld a0, 0(a1); addi a0, a0, 1; c.sd a0, 0(a1); c.ld a2, 0(a1)) #endif RVC_TEST_CASE (8, a0, -15, ori a0, x0, 1; c.addi a0, -16) RVC_TEST_CASE (9, a5, -16, ori a5, x0, 1; c.li a5, -16) -#ifdef __riscv64 +#if __riscv_xlen == 64 RVC_TEST_CASE (10, a0, 0x76543210, ld a0, (a1); c.addiw a0, -1) #endif RVC_TEST_CASE (11, s0, 0xffffffffffffffe1, c.lui s0, 0xfffe1; c.srai s0, 12) -#ifdef __riscv64 +#if __riscv_xlen == 64 RVC_TEST_CASE (12, s0, 0x000fffffffffffe1, c.lui s0, 0xfffe1; c.srli s0, 12) #else RVC_TEST_CASE (12, s0, 0x000fffe1, c.lui s0, 0xfffe1; c.srli s0, 12) @@ -61,7 +61,7 @@ RVTEST_CODE_BEGIN RVC_TEST_CASE (16, s1, 18, li s1, 20; li a0, 6; c.xor s1, a0) RVC_TEST_CASE (17, s1, 22, li s1, 20; li a0, 6; c.or s1, a0) RVC_TEST_CASE (18, s1, 4, li s1, 20; li a0, 6; c.and s1, a0) -#ifdef __riscv64 +#if __riscv_xlen == 64 RVC_TEST_CASE (19, s1, 0xffffffff80000000, li s1, 0x7fffffff; li a0, -1; c.subw s1, a0) RVC_TEST_CASE (20, s1, 0xffffffff80000000, li s1, 0x7fffffff; li a0, 1; c.addw s1, a0) #endif @@ -123,7 +123,7 @@ RVTEST_CODE_BEGIN 2:j fail; \ 1:sub ra, ra, t0) -#ifdef __riscv32 +#if __riscv_xlen == 32 RVC_TEST_CASE (37, ra, -2, \ la t0, 1f; \ li ra, 0; \ @@ -136,7 +136,7 @@ RVTEST_CODE_BEGIN la sp, data RVC_TEST_CASE (40, a2, 0xfffffffffedcba99, c.lwsp a0, 12(sp); addi a0, a0, 1; c.swsp a0, 12(sp); c.lwsp a2, 12(sp)) -#ifdef __riscv64 +#if __riscv_xlen == 64 RVC_TEST_CASE (41, a2, 0xfedcba9976543211, c.ldsp a0, 8(sp); addi a0, a0, 1; c.sdsp a0, 8(sp); c.ldsp a2, 8(sp)) #endif diff --git a/isa/rv64uf/fcvt.S b/isa/rv64uf/fcvt.S index a9a1b59..a41686e 100644 --- a/isa/rv64uf/fcvt.S +++ b/isa/rv64uf/fcvt.S @@ -23,7 +23,7 @@ RVTEST_CODE_BEGIN TEST_INT_FP_OP_S( 4, fcvt.s.wu, 2.0, 2); TEST_INT_FP_OP_S( 5, fcvt.s.wu, 4.2949673e9, -2); -#ifndef __riscv32 +#if __riscv_xlen >= 64 TEST_INT_FP_OP_S( 6, fcvt.s.l, 2.0, 2); TEST_INT_FP_OP_S( 7, fcvt.s.l, -2.0, -2); diff --git a/isa/rv64uf/fcvt_w.S b/isa/rv64uf/fcvt_w.S index bf7878a..cad5cba 100644 --- a/isa/rv64uf/fcvt_w.S +++ b/isa/rv64uf/fcvt_w.S @@ -35,7 +35,7 @@ RVTEST_CODE_BEGIN TEST_FP_INT_OP_S(18, fcvt.wu.s, 0x10, 0, -3e9, rtz); TEST_FP_INT_OP_S(19, fcvt.wu.s, 0x00, 3000000000, 3e9, rtz); -#ifndef __riscv32 +#if __riscv_xlen >= 64 TEST_FP_INT_OP_S(22, fcvt.l.s, 0x01, -1, -1.1, rtz); TEST_FP_INT_OP_S(23, fcvt.l.s, 0x00, -1, -1.0, rtz); TEST_FP_INT_OP_S(24, fcvt.l.s, 0x01, 0, -0.9, rtz); @@ -55,7 +55,7 @@ RVTEST_CODE_BEGIN # test negative NaN, negative infinity conversion TEST_CASE( 42, x1, 0x000000007fffffff, la x1, tdat ; flw f1, 0(x1); fcvt.w.s x1, f1) TEST_CASE( 44, x1, 0xffffffff80000000, la x1, tdat ; flw f1, 8(x1); fcvt.w.s x1, f1) -#ifndef __riscv32 +#if __riscv_xlen >= 64 TEST_CASE( 43, x1, 0x7fffffffffffffff, la x1, tdat ; flw f1, 0(x1); fcvt.l.s x1, f1) TEST_CASE( 45, x1, 0x8000000000000000, la x1, tdat ; flw f1, 8(x1); fcvt.l.s x1, f1) #endif @@ -63,7 +63,7 @@ RVTEST_CODE_BEGIN # test positive NaN, positive infinity conversion TEST_CASE( 52, x1, 0x000000007fffffff, la x1, tdat ; flw f1, 4(x1); fcvt.w.s x1, f1) TEST_CASE( 54, x1, 0x000000007fffffff, la x1, tdat ; flw f1, 12(x1); fcvt.w.s x1, f1) -#ifndef __riscv32 +#if __riscv_xlen >= 64 TEST_CASE( 53, x1, 0x7fffffffffffffff, la x1, tdat ; flw f1, 4(x1); fcvt.l.s x1, f1) TEST_CASE( 55, x1, 0x7fffffffffffffff, la x1, tdat ; flw f1, 12(x1); fcvt.l.s x1, f1) #endif @@ -73,7 +73,7 @@ RVTEST_CODE_BEGIN TEST_CASE( 63, x1, 0xffffffffffffffff, la x1, tdat ; flw f1, 4(x1); fcvt.wu.s x1, f1) TEST_CASE( 64, x1, 0, la x1, tdat ; flw f1, 8(x1); fcvt.wu.s x1, f1) TEST_CASE( 65, x1, 0xffffffffffffffff, la x1, tdat ; flw f1, 12(x1); fcvt.wu.s x1, f1) -#ifndef __riscv32 +#if __riscv_xlen >= 64 TEST_CASE( 66, x1, 0xffffffffffffffff, la x1, tdat ; flw f1, 0(x1); fcvt.lu.s x1, f1) TEST_CASE( 67, x1, 0xffffffffffffffff, la x1, tdat ; flw f1, 4(x1); fcvt.lu.s x1, f1) TEST_CASE( 68, x1, 0, la x1, tdat ; flw f1, 8(x1); fcvt.lu.s x1, f1) diff --git a/isa/rv64ui/sll.S b/isa/rv64ui/sll.S index 31037d1..257aa9d 100644 --- a/isa/rv64ui/sll.S +++ b/isa/rv64ui/sll.S @@ -42,7 +42,7 @@ RVTEST_CODE_BEGIN TEST_RR_OP( 19, sll, 0x0000001090909080, 0x0000000021212121, 0xffffffffffffffc7 ); TEST_RR_OP( 20, sll, 0x0000084848484000, 0x0000000021212121, 0xffffffffffffffce ); -#ifdef __riscv64 +#if __riscv_xlen == 64 TEST_RR_OP( 21, sll, 0x8000000000000000, 0x0000000021212121, 0xffffffffffffffff ); TEST_RR_OP( 50, sll, 0x8000000000000000, 0x0000000000000001, 63 ); TEST_RR_OP( 51, sll, 0xffffff8000000000, 0xffffffffffffffff, 39 ); diff --git a/isa/rv64ui/slli.S b/isa/rv64ui/slli.S index dd02d49..f28ea1c 100644 --- a/isa/rv64ui/slli.S +++ b/isa/rv64ui/slli.S @@ -35,7 +35,7 @@ RVTEST_CODE_BEGIN TEST_IMM_OP( 15, slli, 0x0000084848484000, 0x0000000021212121, 14 ); TEST_IMM_OP( 16, slli, 0x1090909080000000, 0x0000000021212121, 31 ); -#ifdef __riscv64 +#if __riscv_xlen == 64 TEST_RR_OP( 50, sll, 0x8000000000000000, 0x0000000000000001, 63 ); TEST_RR_OP( 51, sll, 0xffffff8000000000, 0xffffffffffffffff, 39 ); TEST_RR_OP( 52, sll, 0x0909080000000000, 0x0000000021212121, 43 ); diff --git a/isa/rv64ui/srl.S b/isa/rv64ui/srl.S index ad5c2e5..c1e936a 100644 --- a/isa/rv64ui/srl.S +++ b/isa/rv64ui/srl.S @@ -18,7 +18,7 @@ RVTEST_CODE_BEGIN #------------------------------------------------------------- #define TEST_SRL(n, v, a) \ - TEST_RR_OP(n, srl, ((v) & ((1 << (_RISCV_SZLONG-1) << 1) - 1)) >> (a), v, a) + TEST_RR_OP(n, srl, ((v) & ((1 << (__riscv_xlen-1) << 1) - 1)) >> (a), v, a) TEST_SRL( 2, 0xffffffff80000000, 0 ); TEST_SRL( 3, 0xffffffff80000000, 1 ); diff --git a/isa/rv64ui/srli.S b/isa/rv64ui/srli.S index eae2532..88ee8d2 100644 --- a/isa/rv64ui/srli.S +++ b/isa/rv64ui/srli.S @@ -18,7 +18,7 @@ RVTEST_CODE_BEGIN #------------------------------------------------------------- #define TEST_SRL(n, v, a) \ - TEST_IMM_OP(n, srli, ((v) & ((1 << (_RISCV_SZLONG-1) << 1) - 1)) >> (a), v, a) + TEST_IMM_OP(n, srli, ((v) & ((1 << (__riscv_xlen-1) << 1) - 1)) >> (a), v, a) TEST_SRL( 2, 0xffffffff80000000, 0 ); TEST_SRL( 3, 0xffffffff80000000, 1 ); -- 2.30.2