From 56fb307eb50a8485dbde0f4cbc28af5e976994a9 Mon Sep 17 00:00:00 2001 From: Tobias Platen Date: Sun, 3 Apr 2022 20:04:02 +0200 Subject: [PATCH] ram addr calculation ram_addr --- wishbone_bram_wrapper.vhdl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/wishbone_bram_wrapper.vhdl b/wishbone_bram_wrapper.vhdl index 9a0358b..fcf528b 100644 --- a/wishbone_bram_wrapper.vhdl +++ b/wishbone_bram_wrapper.vhdl @@ -76,7 +76,7 @@ begin bram_re <= ram_re; -- Wishbone interface - ram_addr <= wishbone_in.adr(ram_addr_bits - 1 downto 0); + ram_addr <= wishbone_in.adr(ram_addr_bits + 2 downto 3); ram_we <= wishbone_in.stb and wishbone_in.cyc and wishbone_in.we; ram_re <= wishbone_in.stb and wishbone_in.cyc and not wishbone_in.we; wishbone_out.stall <= '0'; -- 2.30.2