From 57126f6ef8f6f8517e4ac743e7481cac30535c31 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 17 May 2020 18:10:58 +0100 Subject: [PATCH] simplify field access --- src/soc/logical/main_stage.py | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/soc/logical/main_stage.py b/src/soc/logical/main_stage.py index b50afc27..e740d07a 100644 --- a/src/soc/logical/main_stage.py +++ b/src/soc/logical/main_stage.py @@ -109,8 +109,7 @@ class LogicalMainStage(PipeModBase): ###### cntlz ####### with m.Case(InternalOp.OP_CNTZ): - x_fields = self.fields.instrs['X'] - XO = Signal(x_fields['XO'][0:-1].shape()) + XO = self.fields.FormX.XO[0:-1] m.submodules.countz = countz = ZeroCounter() comb += countz.rs_i.eq(a) comb += countz.is_32bit_i.eq(op.is_32bit) -- 2.30.2