From 57356fb060839f2b2b6f3fa832e2b3937f25900e Mon Sep 17 00:00:00 2001
From: rishucoding <rishucoding@gmail.com>
Date: Tue, 17 Jul 2018 15:22:41 +0530
Subject: [PATCH] revert back to PWMWIDTH from pwmnum in pwm.bsv

---
 src/bsv/bsv_lib/pwm.bsv | 21 +++++++++++----------
 1 file changed, 11 insertions(+), 10 deletions(-)

diff --git a/src/bsv/bsv_lib/pwm.bsv b/src/bsv/bsv_lib/pwm.bsv
index b760f81..ef7d687 100644
--- a/src/bsv/bsv_lib/pwm.bsv
+++ b/src/bsv/bsv_lib/pwm.bsv
@@ -32,6 +32,7 @@ Code inpired by the pwm module at: https://github.com/freecores/pwm
 
 */
 package pwm;
+  `define PWMWIDTH 32
   /*=== Project imports ==*/
   import Clocks::*;
   /*======================*/
@@ -65,16 +66,16 @@ package pwm;
   endinterface
 
   //(*synthesize*)
-  module mkPWM#(Clock ext_clock, numeric type pwmnum_)(PWM);
+  module mkPWM#(Clock ext_clock)(PWM);
 
-    let pwmnum = valueOf(pwmnum_);
+    //let pwmnum = valueOf(pwmnum_);
 
     let bus_clock <- exposeCurrentClock;
     let bus_reset <- exposeCurrentReset;
 
-    Reg#(Bit#(pwmnum_)) period <- mkReg(0);
-    Reg#(Bit#(pwmnum_)) duty_cycle <- mkReg(0);
-    Reg#(Bit#(pwmnum_)) clock_divisor <- mkReg(0);
+    Reg#(Bit#(`PWMWIDTH)) period <- mkReg(0);
+    Reg#(Bit#(`PWMWIDTH)) duty_cycle <- mkReg(0);
+    Reg#(Bit#(`PWMWIDTH)) clock_divisor <- mkReg(0);
     // =========== Control registers ================== //
     Reg#(Bit#(1)) clock_selector <- mkReg(0);     // bit-0
     Reg#(Bit#(1)) pwm_enable <- mkReg(0);         // bit-1
@@ -115,7 +116,7 @@ package pwm;
     // clock divider needs to operate on the
     // external clock. In this case, the divisor value
     // should also come from the same clock domain.
-    Reg#(Bit#(pwmnum_)) clock_divisor_sync <- mkSyncRegFromCC(0, 
+    Reg#(Bit#(`PWMWIDTH)) clock_divisor_sync <- mkSyncRegFromCC(0, 
                                         clock_selection.clock_out);
     rule transfer_data_from_clock_domains;
       clock_divisor_sync <= clock_divisor;
@@ -128,7 +129,7 @@ package pwm;
     // clock domain of the external clock or bus_clock,
     // the divisor (which operates on the bus_clock
     // will have to be synchronized and sent to the divider
-    Ifc_ClockDiv#(pwmnum_) clock_divider <- mkClockDiv(
+    Ifc_ClockDiv#(`PWMWIDTH) clock_divider <- mkClockDiv(
                                         clocked_by clock_selection.clock_out,
                                          reset_by async_reset);
     let downclock = clock_divider.slowclock;
@@ -140,15 +141,15 @@ package pwm;
     // ======= Actual Counter and PWM signal generation ======== //
     Reg#(Bit#(1)) pwm_output <- mkReg(0,clocked_by downclock,
                                         reset_by downreset);
-    Reg#(Bit#(pwmnum_)) rg_counter <-mkReg(0,clocked_by downclock,
+    Reg#(Bit#(`PWMWIDTH)) rg_counter <-mkReg(0,clocked_by downclock,
                                         reset_by downreset);
 
     // create synchronizers for clock domain crossing.
     Reg#(Bit#(1)) sync_pwm_output <- mkSyncRegToCC(0,downclock,downreset);
     ReadOnly#(Bit#(1)) pwm_signal <- mkNullCrossingWire(bus_clock, pwm_output);
     Reg#(Bit#(1)) sync_continous_once <- mkSyncRegFromCC(0,downclock);
-    Reg#(Bit#(pwmnum_)) sync_duty_cycle <- mkSyncRegFromCC(0,downclock);
-    Reg#(Bit#(pwmnum_)) sync_period <- mkSyncRegFromCC(0,downclock);
+    Reg#(Bit#(`PWMWIDTH)) sync_duty_cycle <- mkSyncRegFromCC(0,downclock);
+    Reg#(Bit#(`PWMWIDTH)) sync_period <- mkSyncRegFromCC(0,downclock);
     Reg#(Bit#(1)) sync_pwm_enable <- mkSyncRegFromCC(0,downclock);
     Reg#(Bit#(1)) sync_pwm_start <- mkSyncRegFromCC(0,downclock);
     rule sync_pwm_output_to_default_clock;
-- 
2.30.2