From 574f5885f7d0fce6cb7f3b0bcf476871722d0bc9 Mon Sep 17 00:00:00 2001 From: Eric Botcazou Date: Wed, 19 Sep 2018 10:12:04 +0000 Subject: [PATCH] re PR rtl-optimization/87361 (gcc.target/sparc/20161111-1.c FAILs) PR rtl-optimization/87361 * rtlanal.c (nonzero_bits1): Revert accidental change. From-SVN: r264420 --- gcc/ChangeLog | 5 +++++ gcc/rtlanal.c | 6 +++--- 2 files changed, 8 insertions(+), 3 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 68d8be20e71..1ad3fd05002 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2018-09-19 Eric Botcazou + + PR rtl-optimization/87361 + * rtlanal.c (nonzero_bits1): Revert accidental change. + 2018-09-19 Richard Biener PR tree-optimization/87349 diff --git a/gcc/rtlanal.c b/gcc/rtlanal.c index 366df7c9b3f..e8b6b9c7a42 100644 --- a/gcc/rtlanal.c +++ b/gcc/rtlanal.c @@ -4758,17 +4758,17 @@ nonzero_bits1 (const_rtx x, scalar_int_mode mode, const_rtx known_x, nonzero &= cached_nonzero_bits (SUBREG_REG (x), mode, known_x, known_mode, known_ret); - /* On many CISC machines, accessing an object in a wider mode + /* On many CISC machines, accessing an object in a wider mode causes the high-order bits to become undefined. So they are not known to be zero. */ rtx_code extend_op; if ((!WORD_REGISTER_OPERATIONS /* If this is a typical RISC machine, we only have to worry about the way loads are extended. */ - || !MEM_P (SUBREG_REG (x)) || ((extend_op = load_extend_op (inner_mode)) == SIGN_EXTEND ? val_signbit_known_set_p (inner_mode, nonzero) - : extend_op != ZERO_EXTEND)) + : extend_op != ZERO_EXTEND) + || (!MEM_P (SUBREG_REG (x)) && !REG_P (SUBREG_REG (x)))) && xmode_width > inner_width) nonzero |= (GET_MODE_MASK (GET_MODE (x)) & ~GET_MODE_MASK (inner_mode)); -- 2.30.2