From 575833386fa593c86f362bc385b89ee410895328 Mon Sep 17 00:00:00 2001 From: Jim Wilson Date: Fri, 29 Aug 1997 15:19:58 +0000 Subject: [PATCH] m68k.md (iorsi_zexthi_ashl16): Disable. * m68k/m68k.md (iorsi_zexthi_ashl16): Disable. Fixes m68k codegen problem. From-SVN: r14996 --- gcc/ChangeLog | 4 ++++ gcc/config/m68k/m68k.md | 11 ++++++++++- 2 files changed, 14 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index aba37c09caa..d7c2e502513 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,7 @@ +Thu Aug 28 15:14:46 1997 Jim Wilson + + * m68k/m68k.md (iorsi_zexthi_ashl16): Disable. + 1997-08-27 Andreas Schwab * Makefile.in (config.status): Depend on version.c diff --git a/gcc/config/m68k/m68k.md b/gcc/config/m68k/m68k.md index 456b2778463..2413c648fa5 100644 --- a/gcc/config/m68k/m68k.md +++ b/gcc/config/m68k/m68k.md @@ -3733,12 +3733,21 @@ ;; On all 68k models, this makes faster code in a special case. ;; See also ashlsi_16, ashrsi_16 and lshrsi_16. +;; ??? This pattern can not work as written, because it fails if operand 0 +;; and operand 1 are the same register. This can happen for alternative 1. +;; This will still fail even if an early clobber is added to the output +;; for alternative 1. This is because reload may satisfy the matching +;; constraint by forcing the output to use exactly the same register as +;; operand 2, without noticing that this then causes a conflict with operand 1. +;; Possible fix: check for operand 0/1 overlap, and emit correct but slower +;; code. This should be rare if the early clobber is added. + (define_insn "iorsi_zexthi_ashl16" [(set (match_operand:SI 0 "general_operand" "=&d,d") (ior:SI (zero_extend:SI (match_operand:HI 1 "general_operand" "dmn,dmn")) (ashift:SI (match_operand:SI 2 "general_operand" "o,0") (const_int 16))))] - "" + "0" "* { CC_STATUS_INIT; -- 2.30.2