From 576a27fd552c82008d247991ad7c038e3fa28be1 Mon Sep 17 00:00:00 2001 From: Alyssa Rosenzweig Date: Tue, 30 Apr 2019 02:19:26 +0000 Subject: [PATCH] panfrost/midgard: reg_mode_full -> reg_mode_32, etc In preparation for 8-bit and 64-bit operands, let's not reinforce the 32-bit-centric biases in the ISA. Signed-off-by: Alyssa Rosenzweig --- .../drivers/panfrost/midgard/disassemble.c | 6 +++--- src/gallium/drivers/panfrost/midgard/midgard.h | 8 ++++---- .../drivers/panfrost/midgard/midgard_compile.c | 18 +++++++++--------- 3 files changed, 16 insertions(+), 16 deletions(-) diff --git a/src/gallium/drivers/panfrost/midgard/disassemble.c b/src/gallium/drivers/panfrost/midgard/disassemble.c index 719f5780863..ba1ab2bca5b 100644 --- a/src/gallium/drivers/panfrost/midgard/disassemble.c +++ b/src/gallium/drivers/panfrost/midgard/disassemble.c @@ -229,8 +229,8 @@ print_vector_field(const char *name, uint16_t *words, uint16_t reg_word, midgard_reg_info *reg_info = (midgard_reg_info *)®_word; midgard_vector_alu *alu_field = (midgard_vector_alu *) words; - if (alu_field->reg_mode != midgard_reg_mode_half && - alu_field->reg_mode != midgard_reg_mode_full) { + if (alu_field->reg_mode != midgard_reg_mode_16 && + alu_field->reg_mode != midgard_reg_mode_32) { printf("unknown reg mode %u\n", alu_field->reg_mode); } @@ -245,7 +245,7 @@ print_vector_field(const char *name, uint16_t *words, uint16_t reg_word, bool half, out_half, out_high = false; unsigned mask; - half = (alu_field->reg_mode == midgard_reg_mode_half); + half = (alu_field->reg_mode == midgard_reg_mode_16); if (half) { if (alu_field->mask & 0xF) { diff --git a/src/gallium/drivers/panfrost/midgard/midgard.h b/src/gallium/drivers/panfrost/midgard/midgard.h index cd4882dad1f..e86f517442d 100644 --- a/src/gallium/drivers/panfrost/midgard/midgard.h +++ b/src/gallium/drivers/panfrost/midgard/midgard.h @@ -164,10 +164,10 @@ typedef enum { } midgard_outmod; typedef enum { - midgard_reg_mode_quarter = 0, - midgard_reg_mode_half = 1, - midgard_reg_mode_full = 2, - midgard_reg_mode_double = 3 /* TODO: verify */ + midgard_reg_mode_8 = 0, + midgard_reg_mode_16 = 1, + midgard_reg_mode_32 = 2, + midgard_reg_mode_64 = 3 /* TODO: verify */ } midgard_reg_mode; typedef enum { diff --git a/src/gallium/drivers/panfrost/midgard/midgard_compile.c b/src/gallium/drivers/panfrost/midgard/midgard_compile.c index e1d2edf1670..aa3070839fb 100644 --- a/src/gallium/drivers/panfrost/midgard/midgard_compile.c +++ b/src/gallium/drivers/panfrost/midgard/midgard_compile.c @@ -316,7 +316,7 @@ v_fmov(unsigned src, midgard_vector_alu_src mod, unsigned dest) }, .alu = { .op = midgard_alu_op_fmov, - .reg_mode = midgard_reg_mode_full, + .reg_mode = midgard_reg_mode_32, .dest_override = midgard_dest_override_none, .mask = 0xFF, .src1 = vector_alu_srco_unsigned(zero_alu_src), @@ -1038,7 +1038,7 @@ emit_condition(compiler_context *ctx, nir_src *src, bool for_branch, unsigned co }, .alu = { .op = midgard_alu_op_iand, - .reg_mode = midgard_reg_mode_full, + .reg_mode = midgard_reg_mode_32, .dest_override = midgard_dest_override_none, .mask = (0x3 << 6), /* w */ .src1 = vector_alu_srco_unsigned(alu_src), @@ -1066,7 +1066,7 @@ emit_indirect_offset(compiler_context *ctx, nir_src *src) }, .alu = { .op = midgard_alu_op_imov, - .reg_mode = midgard_reg_mode_full, + .reg_mode = midgard_reg_mode_32, .dest_override = midgard_dest_override_none, .mask = (0x3 << 6), /* w */ .src1 = vector_alu_srco_unsigned(zero_alu_src), @@ -1328,7 +1328,7 @@ emit_alu(compiler_context *ctx, nir_alu_instr *instr) midgard_vector_alu alu = { .op = op, - .reg_mode = midgard_reg_mode_full, + .reg_mode = midgard_reg_mode_32, .dest_override = midgard_dest_override_none, .outmod = outmod, @@ -1576,7 +1576,7 @@ emit_intrinsic(compiler_context *ctx, nir_intrinsic_instr *instr) }, .alu = { .op = midgard_alu_op_u2f, - .reg_mode = midgard_reg_mode_half, + .reg_mode = midgard_reg_mode_16, .dest_override = midgard_dest_override_none, .mask = 0xF, .src1 = vector_alu_srco_unsigned(alu_src), @@ -1601,7 +1601,7 @@ emit_intrinsic(compiler_context *ctx, nir_intrinsic_instr *instr) }, .alu = { .op = midgard_alu_op_fmul, - .reg_mode = midgard_reg_mode_full, + .reg_mode = midgard_reg_mode_32, .dest_override = midgard_dest_override_none, .outmod = midgard_outmod_sat, .mask = 0xFF, @@ -3433,7 +3433,7 @@ emit_blend_epilogue(compiler_context *ctx) }, .alu = { .op = midgard_alu_op_fmul, - .reg_mode = midgard_reg_mode_full, + .reg_mode = midgard_reg_mode_32, .dest_override = midgard_dest_override_lower, .mask = 0xFF, .src1 = vector_alu_srco_unsigned(blank_alu_src), @@ -3458,7 +3458,7 @@ emit_blend_epilogue(compiler_context *ctx) }, .alu = { .op = midgard_alu_op_f2u8, - .reg_mode = midgard_reg_mode_half, + .reg_mode = midgard_reg_mode_16, .dest_override = midgard_dest_override_lower, .outmod = midgard_outmod_pos, .mask = 0xF, @@ -3480,7 +3480,7 @@ emit_blend_epilogue(compiler_context *ctx) }, .alu = { .op = midgard_alu_op_imov, - .reg_mode = midgard_reg_mode_quarter, + .reg_mode = midgard_reg_mode_8, .dest_override = midgard_dest_override_none, .mask = 0xFF, .src1 = vector_alu_srco_unsigned(blank_alu_src), -- 2.30.2