From 576f2efe1643d738a782fdb0add0d7b9dd8b4fb5 Mon Sep 17 00:00:00 2001 From: lkcl Date: Fri, 22 Oct 2021 11:00:41 +0100 Subject: [PATCH] --- 3d_gpu/architecture/dynamic_simd/slice.mdwn | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/3d_gpu/architecture/dynamic_simd/slice.mdwn b/3d_gpu/architecture/dynamic_simd/slice.mdwn index a2b45f515..10a41ac4b 100644 --- a/3d_gpu/architecture/dynamic_simd/slice.mdwn +++ b/3d_gpu/architecture/dynamic_simd/slice.mdwn @@ -122,3 +122,14 @@ So, slicing bits `3:6` of a 32-bit element of `a` must, because we have to match text-align: center !important } + +# Partitioned SIMD Design implications + +Slice is the very first of the entire suite of sub-modules of Partitioned +SimdSignal that requires (and propagates) fixed element widths. All other +sub-modules have up until this point been a fixed *overall* width where the +element widths adapt to completely fill the entire underlying Signal. + +Given that this new width context is then passed through to other SimdSignals, +the entire SimdSignal suite has to adapt to this change in requirements. +It is however not as big an adaptation as it first seems. -- 2.30.2