From 577986c7c45ad00cf0849463f9631b8c1c2a4562 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 28 Mar 2020 20:59:39 +0000 Subject: [PATCH] add sprs --- openpower/isa/sprset.mdwn | 85 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 85 insertions(+) create mode 100644 openpower/isa/sprset.mdwn diff --git a/openpower/isa/sprset.mdwn b/openpower/isa/sprset.mdwn new file mode 100644 index 000000000..e7c827449 --- /dev/null +++ b/openpower/isa/sprset.mdwn @@ -0,0 +1,85 @@ +# Move To Special Purpose Register + +mtspr SPR,RS + + n <- spr[5:9] || spr[0:4] + switch (n) + case(13): see Book III + case(808, 809, 810, 811): + default: + if length(SPR(n)) = 64 then + SPR(n) <- (RS) + else + SPR(n) <- (RS) [32:63] + +# Move From Special Purpose Register + +mfspr RT,SPR + + n <- spr[5:9] || spr[0:4] + switch (n) + case(129): see Book III + case(808, 809, 810, 811): + default: + if length(SPR(n)) = 64 then + RT <- SPR(n) + else + RT <- [0]*32 || SPR(n) + +# Move to CR from XER Extended + +mcrxrx BF + +CR[4×BF+32:4×BF+35] <- XER[OV] || XER[OV32] || XER[CA] || XER[CA32] + +# Move To One Condition Register Field + +mtocrf FXM,RS + + count <- 0 + do i = 0 to 7 + if FXM[i] = 1 then + n <- i + count <- count + 1 + if count = 1 then + CR[4*n+32:4*n+35] <- (RS)[4*n+32:4*n+35] + else CR <- undefined + +# Move To Condition Register Fields + +mtcrf FXM,RS + + mask <- FXM[0]*4 || FXM[1]*4 || ... FXM[7]*4 + CR <- ((RS)[32:63] & mask) | (CR & ¬mask) + +# Move From One Condition Register Field + +mfocrf RT,FXM + + RT <- undefined + count <- 0 + do i = 0 to 7 + if FXM[i] = 1 then + n <- i + count <- count + 1 + if count = 1 then + RT <- [0]*64 + RT[4 *n+32:4*n+35] <- CR[4*n+32:4* n+35] + +# Move From Condition Register + +mfcr RT + + RT <- [0]*32 || CR + +# Set Boolean + +setb RT,BFA + + if CR[4×BFA+32] = 1 then + RT <- 0xFFFF_FFFF_FFFF_FFFF + else if CR[4×BFA+33]=1 then + RT <- 0x0000_0000_0000_0001 + else + RT <- 0x0000_0000_0000_0000 + -- 2.30.2