From 579d3e0304cbac0532cc407993abd7c6a6403fbc Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 30 Mar 2018 07:42:36 +0100
Subject: [PATCH] autopep8 whitespace cleanup

---
 src/bsv/interface_decl.py   |  10 +-
 src/bsv/pinmux_generator.py |   2 +-
 src/migen/safeinmux.py      |  15 ++-
 src/spec/interfaces.py      | 258 +++++++++++++++++++++++++++---------
 4 files changed, 213 insertions(+), 72 deletions(-)

diff --git a/src/bsv/interface_decl.py b/src/bsv/interface_decl.py
index a639c52..1e883c8 100644
--- a/src/bsv/interface_decl.py
+++ b/src/bsv/interface_decl.py
@@ -224,7 +224,7 @@ class Interfaces(UserDict):
                 name = ln[0]
                 count = int(ln[1])
                 spec = self.read_spec(pth, name)
-                self.ifaceadd(name, count, Interface(name, spec, count==1))
+                self.ifaceadd(name, count, Interface(name, spec, count == 1))
 
     def getifacetype(self, fname):
         # finds the interface type, e.g sd_d0 returns "inout"
@@ -288,10 +288,10 @@ mux_interface = MuxInterface('cell', [{'name': 'mux', 'ready': False,
                                        'enabled': False,
                                        'bitspec': '{1}', 'action': True}])
 
-io_interface = IOInterface('io',
-                           [{'name': 'cell', 'enabled': False, 'bitspec': 'GenericIOType'},
-                            {'name': 'inputval', 'action': True, 'io': True},
-                            ])
+io_interface = IOInterface(
+    'io',
+    [{'name': 'cell', 'enabled': False, 'bitspec': 'GenericIOType'},
+     {'name': 'inputval', 'action': True, 'io': True}, ])
 
 # == Peripheral Interface definitions == #
 # these are the interface of the peripherals to the pin mux
diff --git a/src/bsv/pinmux_generator.py b/src/bsv/pinmux_generator.py
index 1a9b86b..b2b3998 100644
--- a/src/bsv/pinmux_generator.py
+++ b/src/bsv/pinmux_generator.py
@@ -128,7 +128,7 @@ def pinmuxgen(pth=None, verify=True):
 ''')
         for cell in p.muxed_cells:
             bsv_file.write(mux_interface.wirefmt(
-                cell[0], 'Bit#('+str(int(math.log(len(cell) - 1, 2)))+')'))
+                cell[0], 'Bit#(' + str(int(math.log(len(cell) - 1, 2))) + ')'))
 
         ifaces.wirefmt(bsv_file)
 
diff --git a/src/migen/safeinmux.py b/src/migen/safeinmux.py
index 3e304e7..70f5b8b 100644
--- a/src/migen/safeinmux.py
+++ b/src/migen/safeinmux.py
@@ -5,9 +5,11 @@ from migen.fhdl.structure import Mux, Signal, Array, Constant, If, Case
 from migen.fhdl import verilog
 from migen.sim.core import run_simulation
 
+
 def orop(x1, x2):
     return x1 | x2
 
+
 class SafeInputMux(Module):
     def __init__(self, inwidth):
         wlog = int(log(inwidth, 2))
@@ -16,13 +18,13 @@ class SafeInputMux(Module):
             self.inputs.append(Signal(1, name_override="input_{}".format(i)))
         self.output = Signal(name_override="output")
         self.selector = Signal(max=inwidth + 1)
-        self.io = set(self.inputs) | set([self.output, self.selector]) 
+        self.io = set(self.inputs) | set([self.output, self.selector])
         sel_r = Signal(max=inwidth + 1)
-        sel25 = Signal(max=1<<inwidth)
+        sel25 = Signal(max=1 << inwidth)
         zero = Constant(0)
         muxes = []
         for i in range(len(self.inputs)):
-            x = Constant(1<<i, inwidth)
+            x = Constant(1 << i, inwidth)
             choose = Signal()
             choose.eq(self.selector & x)
             muxes.append(Mux(self.selector & x, self.inputs[i], zero))
@@ -39,7 +41,8 @@ class SafeInputMux(Module):
                         sel25.eq(0),
                         ).Else(
                             Case(sel_r, d)
-                        )
+        )
+
 
 class Blinker(Module):
     def __init__(self, led, maxperiod1, maxperiod2, select):
@@ -66,9 +69,9 @@ def tb(dut):
     for val in [0, 1]:
         for i in range(4):
             yield dut.inputs[i].eq(val)
-            for sel in [0,1,2,3]:
+            for sel in [0, 1, 2, 3]:
                 yield dut.selector.eq(sel)
-                yield # run one more clock
+                yield  # run one more clock
                 yield
                 s = ''
                 ins = []
diff --git a/src/spec/interfaces.py b/src/spec/interfaces.py
index ceef5b9..4799bb7 100644
--- a/src/spec/interfaces.py
+++ b/src/spec/interfaces.py
@@ -2,6 +2,7 @@
 
 from copy import deepcopy
 
+
 def namesuffix(name, suffix, namelist):
     names = []
     for n in namelist:
@@ -51,43 +52,71 @@ class Pinouts(object):
     def __getitem__(self, k):
         return self.pins[k]
 
-
     def i2s(self, suffix, offs, bank, mux=1, spec=None, limit=None):
         i2spins = ['MCK+', 'BCK+', 'LRCK+', 'DI-', 'DO+']
         # for i in range(4):
         #    i2spins.append("DO%d+" % i)
-        pins = Pins('IIS', i2spins, self.bankspec, suffix, offs, bank, mux, spec, limit,
-                    origsuffix=suffix)
+        pins = Pins(
+            'IIS',
+            i2spins,
+            self.bankspec,
+            suffix,
+            offs,
+            bank,
+            mux,
+            spec,
+            limit,
+            origsuffix=suffix)
         self.pinmerge(pins)
 
-
     def emmc(self, suffix, offs, bank, mux=1, spec=None):
         emmcpins = ['CMD+', 'CLK+']
         for i in range(8):
             emmcpins.append("D%d*" % i)
-        pins = Pins('MMC', emmcpins, self.bankspec, suffix, offs, bank, mux, spec,
-                    origsuffix=suffix)
+        pins = Pins(
+            'MMC',
+            emmcpins,
+            self.bankspec,
+            suffix,
+            offs,
+            bank,
+            mux,
+            spec,
+            origsuffix=suffix)
         self.pinmerge(pins)
 
-
     def sdmmc(self, suffix, offs, bank, mux=1, spec=None,
               start=None, limit=None):
         sdmmcpins = ['CMD+', 'CLK+']
         for i in range(4):
             sdmmcpins.append("D%d*" % i)
         sdmmcpins = sdmmcpins[start:limit]
-        pins = Pins('SD', sdmmcpins, self.bankspec, suffix, offs, bank, mux, spec,
-                    origsuffix=suffix)
+        pins = Pins(
+            'SD',
+            sdmmcpins,
+            self.bankspec,
+            suffix,
+            offs,
+            bank,
+            mux,
+            spec,
+            origsuffix=suffix)
         self.pinmerge(pins)
 
-
     def spi(self, suffix, offs, bank, mux=1, spec=None):
         spipins = ['CLK*', 'NSS*', 'MOSI*', 'MISO*']
-        pins = Pins('SPI', spipins, self.bankspec, suffix, offs, bank, mux, spec,
-                    origsuffix=suffix)
+        pins = Pins(
+            'SPI',
+            spipins,
+            self.bankspec,
+            suffix,
+            offs,
+            bank,
+            mux,
+            spec,
+            origsuffix=suffix)
         self.pinmerge(pins)
 
-
     def quadspi(self, suffix, offs, bank, mux=1, spec=None, limit=None):
         spipins = ['CK*', 'NSS*', 'IO0*', 'IO1*', 'IO2*', 'IO3*']
         pins = Pins(
@@ -103,54 +132,94 @@ class Pinouts(object):
             origsuffix=suffix)
         self.pinmerge(pins)
 
-
     def i2c(self, suffix, offs, bank, mux=1, spec=None):
         spipins = ['SDA*', 'SCL*']
-        pins = Pins('TWI', spipins, self.bankspec, suffix, offs, bank, mux, spec,
-                    origsuffix=suffix)
+        pins = Pins(
+            'TWI',
+            spipins,
+            self.bankspec,
+            suffix,
+            offs,
+            bank,
+            mux,
+            spec,
+            origsuffix=suffix)
         self.pinmerge(pins)
 
-
     def jtag(self, suffix, offs, bank, mux=1, spec=None):
         jtagpins = ['MS+', 'DI-', 'DO+', 'CK+']
-        pins = Pins('JTAG', jtagpins, self.bankspec, suffix, offs, bank, mux, spec,
-                    origsuffix=suffix)
+        pins = Pins(
+            'JTAG',
+            jtagpins,
+            self.bankspec,
+            suffix,
+            offs,
+            bank,
+            mux,
+            spec,
+            origsuffix=suffix)
         self.pinmerge(pins)
 
-
     def uart(self, suffix, offs, bank, mux=1, spec=None):
         uartpins = ['TX+', 'RX-']
-        pins = Pins('UART', uartpins, self.bankspec, suffix, offs, bank, mux, spec,
-                    origsuffix=suffix)
+        pins = Pins(
+            'UART',
+            uartpins,
+            self.bankspec,
+            suffix,
+            offs,
+            bank,
+            mux,
+            spec,
+            origsuffix=suffix)
         self.pinmerge(pins)
 
-
-
     def ulpi(self, suffix, offs, bank, mux=1, spec=None):
         ulpipins = ['CK+', 'DIR+', 'STP+', 'NXT+']
         for i in range(8):
             ulpipins.append('D%d*' % i)
-        pins = Pins('ULPI', ulpipins, self.bankspec, suffix, offs, bank, mux, spec,
-                    origsuffix=suffix)
+        pins = Pins(
+            'ULPI',
+            ulpipins,
+            self.bankspec,
+            suffix,
+            offs,
+            bank,
+            mux,
+            spec,
+            origsuffix=suffix)
         self.pinmerge(pins)
 
-
     def uartfull(self, suffix, offs, bank, mux=1, spec=None):
         uartpins = ['TX+', 'RX-', 'CTS-', 'RTS+']
-        pins = Pins('UARTQ', uartpins, self.bankspec, suffix, offs, bank, mux, spec,
-                    origsuffix=suffix)
+        pins = Pins(
+            'UARTQ',
+            uartpins,
+            self.bankspec,
+            suffix,
+            offs,
+            bank,
+            mux,
+            spec,
+            origsuffix=suffix)
         self.pinmerge(pins)
 
-
     def rgbttl(self, suffix, offs, bank, mux=1, spec=None):
         ttlpins = ['CK+', 'DE+', 'HS+', 'VS+']
         for i in range(24):
             ttlpins.append("D%d+" % i)
-        pins = Pins('LCD', ttlpins, self.bankspec, suffix, offs, bank, mux, spec,
-                    origsuffix=suffix)
+        pins = Pins(
+            'LCD',
+            ttlpins,
+            self.bankspec,
+            suffix,
+            offs,
+            bank,
+            mux,
+            spec,
+            origsuffix=suffix)
         self.pinmerge(pins)
 
-
     def rgmii(self, suffix, offs, bank, mux=1, spec=None):
         buspins = []
         for i in range(4):
@@ -161,11 +230,18 @@ class Pinouts(object):
                     'EMDC+', 'EMDIO*',
                     'ETXEN+', 'ETXCK+', 'ECRS-',
                     'ECOL+', 'ETXERR+']
-        pins = Pins('RG', buspins, self.bankspec, suffix, offs, bank, mux, spec,
-                    origsuffix=suffix)
+        pins = Pins(
+            'RG',
+            buspins,
+            self.bankspec,
+            suffix,
+            offs,
+            bank,
+            mux,
+            spec,
+            origsuffix=suffix)
         self.pinmerge(pins)
 
-
     def flexbus1(self, suffix, offs, bank, mux=1, spec=None, limit=None):
         buspins = []
         for i in range(8):
@@ -179,20 +255,36 @@ class Pinouts(object):
             buspins.append("BWE%d" % i)
         for i in range(2, 6):
             buspins.append("CS%d+" % i)
-        pins = Pins('FB', buspins, self.bankspec, suffix, offs, bank, mux, spec, limit,
-                    origsuffix=suffix)
+        pins = Pins(
+            'FB',
+            buspins,
+            self.bankspec,
+            suffix,
+            offs,
+            bank,
+            mux,
+            spec,
+            limit,
+            origsuffix=suffix)
         self.pinmerge(pins)
 
-
     def flexbus2(self, suffix, offs, bank, mux=1, spec=None, limit=None):
         buspins = []
         for i in range(8, 32):
             buspins.append("AD%d*" % i)
-        pins = Pins('FB', buspins, self.bankspec, suffix, offs, bank, mux, spec, limit,
-                    origsuffix=suffix)
+        pins = Pins(
+            'FB',
+            buspins,
+            self.bankspec,
+            suffix,
+            offs,
+            bank,
+            mux,
+            spec,
+            limit,
+            origsuffix=suffix)
         self.pinmerge(pins)
 
-
     def sdram1(self, suffix, offs, bank, mux=1, spec=None):
         buspins = []
         for i in range(16):
@@ -209,8 +301,16 @@ class Pinouts(object):
             buspins.append("SDRBA%d+" % i)
         buspins += ['SDRCKE+', 'SDRRAS#+', 'SDRCAS#+', 'SDRWE#+',
                     'SDRRST+']
-        pins = Pins('SDR', buspins, self.bankspec, suffix, offs, bank, mux, spec,
-                    origsuffix=suffix)
+        pins = Pins(
+            'SDR',
+            buspins,
+            self.bankspec,
+            suffix,
+            offs,
+            bank,
+            mux,
+            spec,
+            origsuffix=suffix)
         self.pinmerge(pins)
 
     def sdram2(self, suffix, offs, bank, mux=1, spec=None, limit=None):
@@ -219,9 +319,17 @@ class Pinouts(object):
             buspins.append("SDRCS%d#+" % i)
         for i in range(8, 32):
             buspins.append("SDRDQ%d*" % i)
-        pins = Pins('SDR', buspins, self.bankspec, suffix, offs, bank, mux, spec,
-                    limit,
-                    origsuffix=suffix)
+        pins = Pins(
+            'SDR',
+            buspins,
+            self.bankspec,
+            suffix,
+            offs,
+            bank,
+            mux,
+            spec,
+            limit,
+            origsuffix=suffix)
         self.pinmerge(pins)
 
     def mcu8080(self, suffix, offs, bank, mux=1, spec=None):
@@ -236,8 +344,16 @@ class Pinouts(object):
             buspins.append("MCUNRB%d+" % i)
         buspins += ['MCUCD+', 'MCURD+', 'MCUWR+', 'MCUCLE+', 'MCUALE+',
                     'MCURST+']
-        pins = Pins('MCU', buspins, self.bankspec, suffix, offs, bank, mux, spec,
-                    origsuffix=suffix)
+        pins = Pins(
+            'MCU',
+            buspins,
+            self.bankspec,
+            suffix,
+            offs,
+            bank,
+            mux,
+            spec,
+            origsuffix=suffix)
         self.pinmerge(pins)
 
     def _pinbank(self, prefix, suffix, offs, bank, gpiooffs, gpionum=1, mux=1,
@@ -245,31 +361,53 @@ class Pinouts(object):
         gpiopins = []
         for i in range(gpiooffs, gpiooffs + gpionum):
             gpiopins.append("%s%d*" % (bank, i))
-        pins = Pins(prefix, gpiopins, self.bankspec, suffix, offs, bank, mux, spec,
-                    origsuffix=suffix)
+        pins = Pins(
+            prefix,
+            gpiopins,
+            self.bankspec,
+            suffix,
+            offs,
+            bank,
+            mux,
+            spec,
+            origsuffix=suffix)
         self.pinmerge(pins)
 
     def eint(self, suffix, offs, bank, gpiooffs, gpionum=1, mux=1, spec=None):
         gpiopins = []
         for i in range(gpiooffs, gpiooffs + gpionum):
             gpiopins.append("%d*" % (i))
-        pins = Pins('EINT', gpiopins, self.bankspec, suffix, offs, bank, mux, spec,
-                    origsuffix=suffix)
+        pins = Pins(
+            'EINT',
+            gpiopins,
+            self.bankspec,
+            suffix,
+            offs,
+            bank,
+            mux,
+            spec,
+            origsuffix=suffix)
         self.pinmerge(pins)
 
     def pwm(self, suffix, offs, bank, pwmoffs, pwmnum=1, mux=1, spec=None):
         pwmpins = []
         for i in range(pwmoffs, pwmoffs + pwmnum):
             pwmpins.append("%d+" % (i))
-        pins = Pins('PWM', pwmpins, self.bankspec, suffix, offs, bank, mux, spec,
-                    origsuffix=suffix)
+        pins = Pins(
+            'PWM',
+            pwmpins,
+            self.bankspec,
+            suffix,
+            offs,
+            bank,
+            mux,
+            spec,
+            origsuffix=suffix)
         self.pinmerge(pins)
 
-
     def gpio(self, suffix, offs, bank, gpiooffs, gpionum=1, mux=1, spec=None):
         self._pinbank("GPIO%s" % bank, suffix, offs, bank, gpiooffs,
-                                  gpionum, mux=0, spec=None)
-
+                      gpionum, mux=0, spec=None)
 
     def pinmerge(self, fn):
         # hack, store the function specs in the pins dict
@@ -288,7 +426,8 @@ class Pinouts(object):
             specname = fname + suffix
         else:
             specname = fname
-        print "fname bank specname suffix ", fname, bank, specname, repr(suffix)
+        print "fname bank specname suffix ", fname, bank, specname, repr(
+            suffix)
         if specname in self.fnspec[fname]:
             # ok so some declarations may bring in different
             # names at different stages (EINT, PWM, flexbus1/2)
@@ -375,4 +514,3 @@ class Pins(object):
                 res[idx_] = pin
 
         self.pins = res
-
-- 
2.30.2