From 579f368704e340c47957d5fb5aca6ecda6624a69 Mon Sep 17 00:00:00 2001 From: Richard Sandiford Date: Mon, 25 Sep 2017 12:57:49 +0000 Subject: [PATCH] Update interface to TARGET_VECTORIZE_VEC_PERM_CONST_OK This patch makes TARGET_VECTORIZE_VEC_PERM_CONST_OK take the permute vector in the form of a vec_perm_indices instead of an unsigned char *. It follows on from the recent patch that did the same in target-independent code. It was easy to make ARM and AArch64 use vec_perm_indices internally as well, and converting AArch64 helps with SVE. I did try doing the same for the other ports, but the surgery needed was much more invasive and much less obviously correct. 2017-09-22 Richard Sandiford gcc/ * target.def (vec_perm_const_ok): Change sel parameter to vec_perm_indices. * optabs-query.c (can_vec_perm_p): Update accordingly. * doc/tm.texi: Regenerate. * config/aarch64/aarch64.c (expand_vec_perm_d): Change perm to auto_vec_perm_indices and remove separate nelt field. (aarch64_evpc_trn, aarch64_evpc_uzp, aarch64_evpc_zip) (aarch64_evpc_ext, aarch64_evpc_rev, aarch64_evpc_dup) (aarch64_evpc_tbl, aarch64_expand_vec_perm_const_1) (aarch64_expand_vec_perm_const): Update accordingly. (aarch64_vectorize_vec_perm_const_ok): Likewise. Change sel to vec_perm_indices. * config/arm/arm.c (expand_vec_perm_d): Change perm to auto_vec_perm_indices and remove separate nelt field. (arm_evpc_neon_vuzp, arm_evpc_neon_vzip, arm_evpc_neon_vrev) (arm_evpc_neon_vtrn, arm_evpc_neon_vext, arm_evpc_neon_vtbl) (arm_expand_vec_perm_const_1, arm_expand_vec_perm_const): Update accordingly. (arm_vectorize_vec_perm_const_ok): Likewise. Change sel to vec_perm_indices. * config/i386/i386.c (ix86_vectorize_vec_perm_const_ok): Change sel to vec_perm_indices. * config/ia64/ia64.c (ia64_vectorize_vec_perm_const_ok): Likewise. * config/mips/mips.c (mips_vectorize_vec_perm_const_ok): Likewise. * config/powerpcspe/powerpcspe.c (rs6000_vectorize_vec_perm_const_ok): Likewise. * config/rs6000/rs6000.c (rs6000_vectorize_vec_perm_const_ok): Likewise. From-SVN: r253148 --- gcc/ChangeLog | 31 +++++++++++++++++++++++ gcc/config/aarch64/aarch64.c | 40 ++++++++++++++---------------- gcc/config/arm/arm.c | 39 ++++++++++++++--------------- gcc/config/i386/i386.c | 7 +++--- gcc/config/ia64/ia64.c | 10 +++----- gcc/config/mips/mips.c | 7 +++--- gcc/config/powerpcspe/powerpcspe.c | 3 +-- gcc/config/rs6000/rs6000.c | 3 +-- gcc/doc/tm.texi | 2 +- gcc/optabs-query.c | 2 +- gcc/target.def | 2 +- 11 files changed, 83 insertions(+), 63 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index b3dadab4357..b6dd97832f6 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,34 @@ +2017-09-25 Richard Sandiford + + * target.def (vec_perm_const_ok): Change sel parameter to + vec_perm_indices. + * optabs-query.c (can_vec_perm_p): Update accordingly. + * doc/tm.texi: Regenerate. + * config/aarch64/aarch64.c (expand_vec_perm_d): Change perm to + auto_vec_perm_indices and remove separate nelt field. + (aarch64_evpc_trn, aarch64_evpc_uzp, aarch64_evpc_zip) + (aarch64_evpc_ext, aarch64_evpc_rev, aarch64_evpc_dup) + (aarch64_evpc_tbl, aarch64_expand_vec_perm_const_1) + (aarch64_expand_vec_perm_const): Update accordingly. + (aarch64_vectorize_vec_perm_const_ok): Likewise. Change sel + to vec_perm_indices. + * config/arm/arm.c (expand_vec_perm_d): Change perm to + auto_vec_perm_indices and remove separate nelt field. + (arm_evpc_neon_vuzp, arm_evpc_neon_vzip, arm_evpc_neon_vrev) + (arm_evpc_neon_vtrn, arm_evpc_neon_vext, arm_evpc_neon_vtbl) + (arm_expand_vec_perm_const_1, arm_expand_vec_perm_const): Update + accordingly. + (arm_vectorize_vec_perm_const_ok): Likewise. Change sel + to vec_perm_indices. + * config/i386/i386.c (ix86_vectorize_vec_perm_const_ok): Change + sel to vec_perm_indices. + * config/ia64/ia64.c (ia64_vectorize_vec_perm_const_ok): Likewise. + * config/mips/mips.c (mips_vectorize_vec_perm_const_ok): Likewise. + * config/powerpcspe/powerpcspe.c (rs6000_vectorize_vec_perm_const_ok): + Likewise. + * config/rs6000/rs6000.c (rs6000_vectorize_vec_perm_const_ok): + Likewise. + 2017-09-25 Pierre-Marie de Rodat PR debug/82155 diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index 5e26cb70da0..f38540b396a 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -141,8 +141,8 @@ static void aarch64_elf_asm_constructor (rtx, int) ATTRIBUTE_UNUSED; static void aarch64_elf_asm_destructor (rtx, int) ATTRIBUTE_UNUSED; static void aarch64_override_options_after_change (void); static bool aarch64_vector_mode_supported_p (machine_mode); -static bool aarch64_vectorize_vec_perm_const_ok (machine_mode vmode, - const unsigned char *sel); +static bool aarch64_vectorize_vec_perm_const_ok (machine_mode, + vec_perm_indices); static int aarch64_address_cost (rtx, machine_mode, addr_space_t, bool); static bool aarch64_builtin_support_vector_misalignment (machine_mode mode, const_tree type, @@ -13146,9 +13146,8 @@ aarch64_split_combinev16qi (rtx operands[3]) struct expand_vec_perm_d { rtx target, op0, op1; - unsigned char perm[MAX_VECT_LEN]; + auto_vec_perm_indices perm; machine_mode vmode; - unsigned char nelt; bool one_vector_p; bool testing_p; }; @@ -13231,7 +13230,7 @@ aarch64_expand_vec_perm (rtx target, rtx op0, rtx op1, rtx sel) static bool aarch64_evpc_trn (struct expand_vec_perm_d *d) { - unsigned int i, odd, mask, nelt = d->nelt; + unsigned int i, odd, mask, nelt = d->perm.length (); rtx out, in0, in1, x; rtx (*gen) (rtx, rtx, rtx); machine_mode vmode = d->vmode; @@ -13319,7 +13318,7 @@ aarch64_evpc_trn (struct expand_vec_perm_d *d) static bool aarch64_evpc_uzp (struct expand_vec_perm_d *d) { - unsigned int i, odd, mask, nelt = d->nelt; + unsigned int i, odd, mask, nelt = d->perm.length (); rtx out, in0, in1, x; rtx (*gen) (rtx, rtx, rtx); machine_mode vmode = d->vmode; @@ -13406,7 +13405,7 @@ aarch64_evpc_uzp (struct expand_vec_perm_d *d) static bool aarch64_evpc_zip (struct expand_vec_perm_d *d) { - unsigned int i, high, mask, nelt = d->nelt; + unsigned int i, high, mask, nelt = d->perm.length (); rtx out, in0, in1, x; rtx (*gen) (rtx, rtx, rtx); machine_mode vmode = d->vmode; @@ -13499,7 +13498,7 @@ aarch64_evpc_zip (struct expand_vec_perm_d *d) static bool aarch64_evpc_ext (struct expand_vec_perm_d *d) { - unsigned int i, nelt = d->nelt; + unsigned int i, nelt = d->perm.length (); rtx (*gen) (rtx, rtx, rtx, rtx); rtx offset; @@ -13563,7 +13562,7 @@ aarch64_evpc_ext (struct expand_vec_perm_d *d) static bool aarch64_evpc_rev (struct expand_vec_perm_d *d) { - unsigned int i, j, diff, nelt = d->nelt; + unsigned int i, j, diff, nelt = d->perm.length (); rtx (*gen) (rtx, rtx); if (!d->one_vector_p) @@ -13641,7 +13640,7 @@ aarch64_evpc_dup (struct expand_vec_perm_d *d) rtx out = d->target; rtx in0; machine_mode vmode = d->vmode; - unsigned int i, elt, nelt = d->nelt; + unsigned int i, elt, nelt = d->perm.length (); rtx lane; elt = d->perm[0]; @@ -13686,7 +13685,7 @@ aarch64_evpc_tbl (struct expand_vec_perm_d *d) { rtx rperm[MAX_VECT_LEN], sel; machine_mode vmode = d->vmode; - unsigned int i, nelt = d->nelt; + unsigned int i, nelt = d->perm.length (); if (d->testing_p) return true; @@ -13720,12 +13719,11 @@ aarch64_expand_vec_perm_const_1 (struct expand_vec_perm_d *d) /* The pattern matching functions above are written to look for a small number to begin the sequence (0, 1, N/2). If we begin with an index from the second operand, we can swap the operands. */ - if (d->perm[0] >= d->nelt) + unsigned int nelt = d->perm.length (); + if (d->perm[0] >= nelt) { - unsigned i, nelt = d->nelt; - gcc_assert (nelt == (nelt & -nelt)); - for (i = 0; i < nelt; ++i) + for (unsigned int i = 0; i < nelt; ++i) d->perm[i] ^= nelt; /* Keep the same index, but in the other vector. */ std::swap (d->op0, d->op1); @@ -13764,15 +13762,16 @@ aarch64_expand_vec_perm_const (rtx target, rtx op0, rtx op1, rtx sel) d.vmode = GET_MODE (target); gcc_assert (VECTOR_MODE_P (d.vmode)); - d.nelt = nelt = GET_MODE_NUNITS (d.vmode); d.testing_p = false; + nelt = GET_MODE_NUNITS (d.vmode); + d.perm.reserve (nelt); for (i = which = 0; i < nelt; ++i) { rtx e = XVECEXP (sel, 0, i); int ei = INTVAL (e) & (2 * nelt - 1); which |= (ei < nelt ? 1 : 2); - d.perm[i] = ei; + d.perm.quick_push (ei); } switch (which) @@ -13807,19 +13806,18 @@ aarch64_expand_vec_perm_const (rtx target, rtx op0, rtx op1, rtx sel) } static bool -aarch64_vectorize_vec_perm_const_ok (machine_mode vmode, - const unsigned char *sel) +aarch64_vectorize_vec_perm_const_ok (machine_mode vmode, vec_perm_indices sel) { struct expand_vec_perm_d d; unsigned int i, nelt, which; bool ret; d.vmode = vmode; - d.nelt = nelt = GET_MODE_NUNITS (d.vmode); d.testing_p = true; - memcpy (d.perm, sel, nelt); + d.perm.safe_splice (sel); /* Calculate whether all elements are in one vector. */ + nelt = sel.length (); for (i = which = 0; i < nelt; ++i) { unsigned char e = d.perm[i]; diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 3e5438ac5c4..3671616cfa7 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -287,8 +287,7 @@ static int arm_cortex_a5_branch_cost (bool, bool); static int arm_cortex_m_branch_cost (bool, bool); static int arm_cortex_m7_branch_cost (bool, bool); -static bool arm_vectorize_vec_perm_const_ok (machine_mode vmode, - const unsigned char *sel); +static bool arm_vectorize_vec_perm_const_ok (machine_mode, vec_perm_indices); static bool aarch_macro_fusion_pair_p (rtx_insn*, rtx_insn*); @@ -28657,9 +28656,8 @@ arm_split_atomic_op (enum rtx_code code, rtx old_out, rtx new_out, rtx mem, struct expand_vec_perm_d { rtx target, op0, op1; - unsigned char perm[MAX_VECT_LEN]; + auto_vec_perm_indices perm; machine_mode vmode; - unsigned char nelt; bool one_vector_p; bool testing_p; }; @@ -28766,7 +28764,7 @@ neon_pair_endian_lane_map (machine_mode mode, int lane) static bool arm_evpc_neon_vuzp (struct expand_vec_perm_d *d) { - unsigned int i, odd, mask, nelt = d->nelt; + unsigned int i, odd, mask, nelt = d->perm.length (); rtx out0, out1, in0, in1; rtx (*gen)(rtx, rtx, rtx, rtx); int first_elem; @@ -28778,7 +28776,7 @@ arm_evpc_neon_vuzp (struct expand_vec_perm_d *d) /* arm_expand_vec_perm_const_1 () helpfully swaps the operands for the big endian pattern on 64 bit vectors, so we correct for that. */ swap_nelt = BYTES_BIG_ENDIAN && !d->one_vector_p - && GET_MODE_SIZE (d->vmode) == 8 ? d->nelt : 0; + && GET_MODE_SIZE (d->vmode) == 8 ? nelt : 0; first_elem = d->perm[neon_endian_lane_map (d->vmode, 0)] ^ swap_nelt; @@ -28837,7 +28835,7 @@ arm_evpc_neon_vuzp (struct expand_vec_perm_d *d) static bool arm_evpc_neon_vzip (struct expand_vec_perm_d *d) { - unsigned int i, high, mask, nelt = d->nelt; + unsigned int i, high, mask, nelt = d->perm.length (); rtx out0, out1, in0, in1; rtx (*gen)(rtx, rtx, rtx, rtx); int first_elem; @@ -28912,7 +28910,7 @@ arm_evpc_neon_vzip (struct expand_vec_perm_d *d) static bool arm_evpc_neon_vrev (struct expand_vec_perm_d *d) { - unsigned int i, j, diff, nelt = d->nelt; + unsigned int i, j, diff, nelt = d->perm.length (); rtx (*gen)(rtx, rtx); if (!d->one_vector_p) @@ -28988,7 +28986,7 @@ arm_evpc_neon_vrev (struct expand_vec_perm_d *d) static bool arm_evpc_neon_vtrn (struct expand_vec_perm_d *d) { - unsigned int i, odd, mask, nelt = d->nelt; + unsigned int i, odd, mask, nelt = d->perm.length (); rtx out0, out1, in0, in1; rtx (*gen)(rtx, rtx, rtx, rtx); @@ -29054,7 +29052,7 @@ arm_evpc_neon_vtrn (struct expand_vec_perm_d *d) static bool arm_evpc_neon_vext (struct expand_vec_perm_d *d) { - unsigned int i, nelt = d->nelt; + unsigned int i, nelt = d->perm.length (); rtx (*gen) (rtx, rtx, rtx, rtx); rtx offset; @@ -29128,7 +29126,7 @@ arm_evpc_neon_vtbl (struct expand_vec_perm_d *d) { rtx rperm[MAX_VECT_LEN], sel; machine_mode vmode = d->vmode; - unsigned int i, nelt = d->nelt; + unsigned int i, nelt = d->perm.length (); /* TODO: ARM's VTBL indexing is little-endian. In order to handle GCC's numbering of elements for big-endian, we must reverse the order. */ @@ -29165,11 +29163,10 @@ arm_expand_vec_perm_const_1 (struct expand_vec_perm_d *d) /* The pattern matching functions above are written to look for a small number to begin the sequence (0, 1, N/2). If we begin with an index from the second operand, we can swap the operands. */ - if (d->perm[0] >= d->nelt) + unsigned int nelt = d->perm.length (); + if (d->perm[0] >= nelt) { - unsigned i, nelt = d->nelt; - - for (i = 0; i < nelt; ++i) + for (unsigned int i = 0; i < nelt; ++i) d->perm[i] = (d->perm[i] + nelt) & (2 * nelt - 1); std::swap (d->op0, d->op1); @@ -29204,15 +29201,16 @@ arm_expand_vec_perm_const (rtx target, rtx op0, rtx op1, rtx sel) d.vmode = GET_MODE (target); gcc_assert (VECTOR_MODE_P (d.vmode)); - d.nelt = nelt = GET_MODE_NUNITS (d.vmode); d.testing_p = false; + nelt = GET_MODE_NUNITS (d.vmode); + d.perm.reserve (nelt); for (i = which = 0; i < nelt; ++i) { rtx e = XVECEXP (sel, 0, i); int ei = INTVAL (e) & (2 * nelt - 1); which |= (ei < nelt ? 1 : 2); - d.perm[i] = ei; + d.perm.quick_push (ei); } switch (which) @@ -29249,19 +29247,18 @@ arm_expand_vec_perm_const (rtx target, rtx op0, rtx op1, rtx sel) /* Implement TARGET_VECTORIZE_VEC_PERM_CONST_OK. */ static bool -arm_vectorize_vec_perm_const_ok (machine_mode vmode, - const unsigned char *sel) +arm_vectorize_vec_perm_const_ok (machine_mode vmode, vec_perm_indices sel) { struct expand_vec_perm_d d; unsigned int i, nelt, which; bool ret; d.vmode = vmode; - d.nelt = nelt = GET_MODE_NUNITS (d.vmode); d.testing_p = true; - memcpy (d.perm, sel, nelt); + d.perm.safe_splice (sel); /* Categorize the set of elements in the selector. */ + nelt = GET_MODE_NUNITS (d.vmode); for (i = which = 0; i < nelt; ++i) { unsigned char e = d.perm[i]; diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index 293287c8af4..29b5a9c1bd8 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -50032,8 +50032,7 @@ ix86_expand_vec_perm_const (rtx operands[4]) /* Implement targetm.vectorize.vec_perm_const_ok. */ static bool -ix86_vectorize_vec_perm_const_ok (machine_mode vmode, - const unsigned char *sel) +ix86_vectorize_vec_perm_const_ok (machine_mode vmode, vec_perm_indices sel) { struct expand_vec_perm_d d; unsigned int i, nelt, which; @@ -50104,11 +50103,11 @@ ix86_vectorize_vec_perm_const_ok (machine_mode vmode, /* Extract the values from the vector CST into the permutation array in D. */ - memcpy (d.perm, sel, nelt); for (i = which = 0; i < nelt; ++i) { - unsigned char e = d.perm[i]; + unsigned char e = sel[i]; gcc_assert (e < 2 * nelt); + d.perm[i] = e; which |= (e < nelt ? 1 : 2); } diff --git a/gcc/config/ia64/ia64.c b/gcc/config/ia64/ia64.c index f34f2f85247..5573f27af37 100644 --- a/gcc/config/ia64/ia64.c +++ b/gcc/config/ia64/ia64.c @@ -333,8 +333,7 @@ static machine_mode ia64_get_reg_raw_mode (int regno); static section * ia64_hpux_function_section (tree, enum node_frequency, bool, bool); -static bool ia64_vectorize_vec_perm_const_ok (machine_mode vmode, - const unsigned char *sel); +static bool ia64_vectorize_vec_perm_const_ok (machine_mode, vec_perm_indices); static unsigned int ia64_hard_regno_nregs (unsigned int, machine_mode); static bool ia64_hard_regno_mode_ok (unsigned int, machine_mode); @@ -11824,8 +11823,7 @@ ia64_expand_vec_perm_const (rtx operands[4]) /* Implement targetm.vectorize.vec_perm_const_ok. */ static bool -ia64_vectorize_vec_perm_const_ok (machine_mode vmode, - const unsigned char *sel) +ia64_vectorize_vec_perm_const_ok (machine_mode vmode, vec_perm_indices sel) { struct expand_vec_perm_d d; unsigned int i, nelt, which; @@ -11837,10 +11835,10 @@ ia64_vectorize_vec_perm_const_ok (machine_mode vmode, /* Extract the values from the vector CST into the permutation array in D. */ - memcpy (d.perm, sel, nelt); for (i = which = 0; i < nelt; ++i) { - unsigned char e = d.perm[i]; + unsigned char e = sel[i]; + d.perm[i] = e; gcc_assert (e < 2 * nelt); which |= (e < nelt ? 1 : 2); } diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c index 8643cb9ad30..a71732e047b 100644 --- a/gcc/config/mips/mips.c +++ b/gcc/config/mips/mips.c @@ -21470,8 +21470,7 @@ mips_sched_reassociation_width (unsigned int opc ATTRIBUTE_UNUSED, /* Implement TARGET_VECTORIZE_VEC_PERM_CONST_OK. */ static bool -mips_vectorize_vec_perm_const_ok (machine_mode vmode, - const unsigned char *sel) +mips_vectorize_vec_perm_const_ok (machine_mode vmode, vec_perm_indices sel) { struct expand_vec_perm_d d; unsigned int i, nelt, which; @@ -21480,12 +21479,12 @@ mips_vectorize_vec_perm_const_ok (machine_mode vmode, d.vmode = vmode; d.nelt = nelt = GET_MODE_NUNITS (d.vmode); d.testing_p = true; - memcpy (d.perm, sel, nelt); /* Categorize the set of elements in the selector. */ for (i = which = 0; i < nelt; ++i) { - unsigned char e = d.perm[i]; + unsigned char e = sel[i]; + d.perm[i] = e; gcc_assert (e < 2 * nelt); which |= (e < nelt ? 1 : 2); } diff --git a/gcc/config/powerpcspe/powerpcspe.c b/gcc/config/powerpcspe/powerpcspe.c index c7ccda10f7b..26692aa8a69 100644 --- a/gcc/config/powerpcspe/powerpcspe.c +++ b/gcc/config/powerpcspe/powerpcspe.c @@ -38731,8 +38731,7 @@ rs6000_expand_vec_perm_const (rtx operands[4]) /* Test whether a constant permutation is supported. */ static bool -rs6000_vectorize_vec_perm_const_ok (machine_mode vmode, - const unsigned char *sel) +rs6000_vectorize_vec_perm_const_ok (machine_mode vmode, vec_perm_indices sel) { /* AltiVec (and thus VSX) can handle arbitrary permutations. */ if (TARGET_ALTIVEC) diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index e5ef63889b7..9198e9ebeba 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -35594,8 +35594,7 @@ rs6000_expand_vec_perm_const (rtx operands[4]) /* Test whether a constant permutation is supported. */ static bool -rs6000_vectorize_vec_perm_const_ok (machine_mode vmode, - const unsigned char *sel) +rs6000_vectorize_vec_perm_const_ok (machine_mode vmode, vec_perm_indices sel) { /* AltiVec (and thus VSX) can handle arbitrary permutations. */ if (TARGET_ALTIVEC) diff --git a/gcc/doc/tm.texi b/gcc/doc/tm.texi index 1f8c0f12942..c2493cf6251 100644 --- a/gcc/doc/tm.texi +++ b/gcc/doc/tm.texi @@ -5774,7 +5774,7 @@ correct for most targets. Return true if vector alignment is reachable (by peeling N iterations) for the given scalar type @var{type}. @var{is_packed} is false if the scalar access using @var{type} is known to be naturally aligned. @end deftypefn -@deftypefn {Target Hook} bool TARGET_VECTORIZE_VEC_PERM_CONST_OK (machine_mode, const unsigned char *@var{sel}) +@deftypefn {Target Hook} bool TARGET_VECTORIZE_VEC_PERM_CONST_OK (machine_mode, @var{vec_perm_indices}) Return true if a vector created for @code{vec_perm_const} is valid. @end deftypefn diff --git a/gcc/optabs-query.c b/gcc/optabs-query.c index ced6f57f4c2..204ca60249f 100644 --- a/gcc/optabs-query.c +++ b/gcc/optabs-query.c @@ -367,7 +367,7 @@ can_vec_perm_p (machine_mode mode, bool variable, vec_perm_indices *sel) if (direct_optab_handler (vec_perm_const_optab, mode) != CODE_FOR_nothing && (sel == NULL || targetm.vectorize.vec_perm_const_ok == NULL - || targetm.vectorize.vec_perm_const_ok (mode, &(*sel)[0]))) + || targetm.vectorize.vec_perm_const_ok (mode, *sel))) return true; } diff --git a/gcc/target.def b/gcc/target.def index 9e5ddc00a43..42fd0b1854a 100644 --- a/gcc/target.def +++ b/gcc/target.def @@ -1847,7 +1847,7 @@ DEFHOOK DEFHOOK (vec_perm_const_ok, "Return true if a vector created for @code{vec_perm_const} is valid.", - bool, (machine_mode, const unsigned char *sel), + bool, (machine_mode, vec_perm_indices), NULL) /* Return true if the target supports misaligned store/load of a -- 2.30.2