From 579feaba4e5d220baa76525af534007ba88c5389 Mon Sep 17 00:00:00 2001 From: whitequark Date: Fri, 14 Dec 2018 20:58:29 +0000 Subject: [PATCH] =?utf8?q?fhdl.ir:=20Fragment.{drive=E2=86=92add=5Fdriver}?= MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit --- nmigen/fhdl/dsl.py | 2 +- nmigen/fhdl/ir.py | 2 +- nmigen/fhdl/xfrm.py | 4 ++-- nmigen/test/test_fhdl_ir.py | 4 ++-- nmigen/test/test_fhdl_xfrm.py | 26 +++++++++++++------------- nmigen/test/test_sim.py | 2 +- 6 files changed, 20 insertions(+), 20 deletions(-) diff --git a/nmigen/fhdl/dsl.py b/nmigen/fhdl/dsl.py index 8bbcdc3..72323bb 100644 --- a/nmigen/fhdl/dsl.py +++ b/nmigen/fhdl/dsl.py @@ -274,7 +274,7 @@ class Module(_ModuleBuilderRoot): fragment.add_subfragment(submodule.get_fragment(platform), name) fragment.add_statements(self._statements) for signal, domain in self._driving.items(): - fragment.drive(signal, domain) + fragment.add_driver(signal, domain) return fragment get_fragment = lower diff --git a/nmigen/fhdl/ir.py b/nmigen/fhdl/ir.py index 7004925..dbac817 100644 --- a/nmigen/fhdl/ir.py +++ b/nmigen/fhdl/ir.py @@ -24,7 +24,7 @@ class Fragment: def iter_ports(self): yield from self.ports.keys() - def drive(self, signal, domain=None): + def add_driver(self, signal, domain=None): if domain not in self.drivers: self.drivers[domain] = ValueSet() self.drivers[domain].add(signal) diff --git a/nmigen/fhdl/xfrm.py b/nmigen/fhdl/xfrm.py index bbfe5cf..d6dbac8 100644 --- a/nmigen/fhdl/xfrm.py +++ b/nmigen/fhdl/xfrm.py @@ -119,7 +119,7 @@ class FragmentTransformer: def map_drivers(self, fragment, new_fragment): for domain, signal in fragment.iter_drivers(): - new_fragment.drive(signal, domain) + new_fragment.add_driver(signal, domain) def on_fragment(self, fragment): new_fragment = Fragment() @@ -165,7 +165,7 @@ class DomainRenamer(FragmentTransformer, ValueTransformer, StatementTransformer) if domain in self.domain_map: domain = self.domain_map[domain] for signal in signals: - new_fragment.drive(signal, domain) + new_fragment.add_driver(signal, domain) class DomainLowerer(FragmentTransformer, ValueTransformer, StatementTransformer): diff --git a/nmigen/test/test_fhdl_ir.py b/nmigen/test/test_fhdl_ir.py index ddd1821..3068af4 100644 --- a/nmigen/test/test_fhdl_ir.py +++ b/nmigen/test/test_fhdl_ir.py @@ -109,7 +109,7 @@ class FragmentPortsTestCase(FHDLTestCase): self.c1.eq(self.s1) ) f.add_domains(sync) - f.drive(self.c1, "sync") + f.add_driver(self.c1, "sync") f._propagate_ports(ports=()) self.assertEqual(f.ports, ValueDict([ @@ -125,7 +125,7 @@ class FragmentPortsTestCase(FHDLTestCase): self.c1.eq(self.s1) ) f.add_domains(sync) - f.drive(self.c1, "sync") + f.add_driver(self.c1, "sync") f._propagate_ports(ports=()) self.assertEqual(f.ports, ValueDict([ diff --git a/nmigen/test/test_fhdl_xfrm.py b/nmigen/test/test_fhdl_xfrm.py index ca3c242..861dcd0 100644 --- a/nmigen/test/test_fhdl_xfrm.py +++ b/nmigen/test/test_fhdl_xfrm.py @@ -23,9 +23,9 @@ class DomainRenamerTestCase(FHDLTestCase): self.s4.eq(ClockSignal("other")), self.s5.eq(ResetSignal("other")), ) - f.drive(self.s1, None) - f.drive(self.s2, None) - f.drive(self.s3, "sync") + f.add_driver(self.s1, None) + f.add_driver(self.s2, None) + f.add_driver(self.s3, "sync") f = DomainRenamer("pix")(f) self.assertRepr(f.statements, """ @@ -170,7 +170,7 @@ class ResetInserterTestCase(FHDLTestCase): f.add_statements( self.s1.eq(1) ) - f.drive(self.s1, "sync") + f.add_driver(self.s1, "sync") f = ResetInserter(self.c1)(f) self.assertRepr(f.statements, """ @@ -189,8 +189,8 @@ class ResetInserterTestCase(FHDLTestCase): self.s2.eq(0), ) f.add_domains(ClockDomain("sync")) - f.drive(self.s1, "sync") - f.drive(self.s2, "pix") + f.add_driver(self.s1, "sync") + f.add_driver(self.s2, "pix") f = ResetInserter({"pix": self.c1})(f) self.assertRepr(f.statements, """ @@ -208,7 +208,7 @@ class ResetInserterTestCase(FHDLTestCase): f.add_statements( self.s2.eq(0) ) - f.drive(self.s2, "sync") + f.add_driver(self.s2, "sync") f = ResetInserter(self.c1)(f) self.assertRepr(f.statements, """ @@ -225,7 +225,7 @@ class ResetInserterTestCase(FHDLTestCase): f.add_statements( self.s3.eq(0) ) - f.drive(self.s3, "sync") + f.add_driver(self.s3, "sync") f = ResetInserter(self.c1)(f) self.assertRepr(f.statements, """ @@ -250,7 +250,7 @@ class CEInserterTestCase(FHDLTestCase): f.add_statements( self.s1.eq(1) ) - f.drive(self.s1, "sync") + f.add_driver(self.s1, "sync") f = CEInserter(self.c1)(f) self.assertRepr(f.statements, """ @@ -268,8 +268,8 @@ class CEInserterTestCase(FHDLTestCase): self.s1.eq(1), self.s2.eq(0), ) - f.drive(self.s1, "sync") - f.drive(self.s2, "pix") + f.add_driver(self.s1, "sync") + f.add_driver(self.s2, "pix") f = CEInserter({"pix": self.c1})(f) self.assertRepr(f.statements, """ @@ -287,13 +287,13 @@ class CEInserterTestCase(FHDLTestCase): f1.add_statements( self.s1.eq(1) ) - f1.drive(self.s1, "sync") + f1.add_driver(self.s1, "sync") f2 = Fragment() f2.add_statements( self.s2.eq(1) ) - f2.drive(self.s2, "sync") + f2.add_driver(self.s2, "sync") f1.add_subfragment(f2) f1 = CEInserter(self.c1)(f1) diff --git a/nmigen/test/test_sim.py b/nmigen/test/test_sim.py index 4b29c75..ec41986 100644 --- a/nmigen/test/test_sim.py +++ b/nmigen/test/test_sim.py @@ -14,7 +14,7 @@ class SimulatorUnitTestCase(FHDLTestCase): frag = Fragment() frag.add_statements(osig.eq(stmt(*isigs))) - frag.drive(osig) + frag.add_driver(osig) with Simulator(frag, vcd_file =open("test.vcd", "w"), -- 2.30.2