From 57c95a3889819a7b3e3565c17744582532af9114 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 19 Jun 2019 16:02:18 +0100 Subject: [PATCH] add SV VLIW idea --- simple_v_extension/specification.mdwn | 1 + 1 file changed, 1 insertion(+) diff --git a/simple_v_extension/specification.mdwn b/simple_v_extension/specification.mdwn index 3d0838a78..bbed33931 100644 --- a/simple_v_extension/specification.mdwn +++ b/simple_v_extension/specification.mdwn @@ -2233,6 +2233,7 @@ Reminder of the variable-length format from Section 1.5 of the RISC-V ISA: | base+4 | base+2 | base | number of bits | | ------ | ---------------- | ---------------- | -------------------------- | | ..xxxx | xxxxxxxxxxxxxxxx | xnnnxxxxx1111111 | (80+16\*nnn)-bit, nnn!=111 | +| {ops}{Pred}{Reg}{VL} || SV Prefix | | Notes: -- 2.30.2