From 57d25328c3c97a1386e2d25312f9d55ebff6157e Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 8 Apr 2021 21:21:09 +0100 Subject: [PATCH] shrink JTAG master bus to 32-bit (match with litex) --- src/soc/debug/jtag.py | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/src/soc/debug/jtag.py b/src/soc/debug/jtag.py index c2a6f095..52d236f4 100644 --- a/src/soc/debug/jtag.py +++ b/src/soc/debug/jtag.py @@ -62,7 +62,8 @@ class Pins: class JTAG(DMITAP, Pins): - def __init__(self, pinset, wb_data_wid=64): + # 32-bit data width here so that it matches with litex + def __init__(self, pinset, wb_data_wid=32): DMITAP.__init__(self, ir_width=4) Pins.__init__(self, pinset) @@ -80,8 +81,9 @@ class JTAG(DMITAP, Pins): self.sr = self.add_shiftreg(ircode=4, length=3) # create and connect wishbone - self.wb = self.add_wishbone(ircodes=[5, 6, 7], features={'err'}, - address_width=29, data_width=wb_data_wid, + self.wb = self.add_wishbone(ircodes=[5, 6, 7], + features={'err', 'stall'}, + address_width=30, data_width=wb_data_wid, granularity=8, # 8-bit wide name="jtag_wb") @@ -110,6 +112,10 @@ class JTAG(DMITAP, Pins): with m.If(self.sr_en.ie): m.d.comb += self.sr_en.i.eq(en_sigs) + # create a fake "stall" + wb = self.wb + m.d.comb += wb.stall.eq(wb.cyc & ~wb.ack) # No burst support + return m def external_ports(self): -- 2.30.2