From 57e951f6eae1de88988a9b13035c07985a0bcd73 Mon Sep 17 00:00:00 2001
From: Gabe Black <gabeblack@google.com>
Date: Mon, 4 Nov 2019 16:27:34 -0800
Subject: [PATCH] arch,cpu: Get rid of ISA_HAS_CC_REGS and its associated
 ifdefs.

This conditional compilation was unnecessary and makes gem5 more
brittle and harder to understand.

Change-Id: I63abaf2668252c988cdd4626ff6a462eb6f54b04
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22544
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
---
 src/arch/arm/registers.hh |  2 --
 src/arch/x86/registers.hh |  2 --
 src/cpu/simple_thread.hh  | 27 ---------------------------
 src/cpu/thread_context.cc | 24 ++++++++++++------------
 4 files changed, 12 insertions(+), 43 deletions(-)

diff --git a/src/arch/arm/registers.hh b/src/arch/arm/registers.hh
index a97a4ce25..84f382b9c 100644
--- a/src/arch/arm/registers.hh
+++ b/src/arch/arm/registers.hh
@@ -102,8 +102,6 @@ const int INTRLVREG1 = INTRLVREG0 + 1;
 const int INTRLVREG2 = INTRLVREG0 + 2;
 const int INTRLVREG3 = INTRLVREG0 + 3;
 
-#define ISA_HAS_CC_REGS
-
 const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumVecRegs +
     NumVecPredRegs + NumMiscRegs;
 
diff --git a/src/arch/x86/registers.hh b/src/arch/x86/registers.hh
index 0590abe49..479eda118 100644
--- a/src/arch/x86/registers.hh
+++ b/src/arch/x86/registers.hh
@@ -60,8 +60,6 @@ const int NumIntArchRegs = NUM_INTREGS;
 const int NumIntRegs = NumIntArchRegs + NumMicroIntRegs + NumImplicitIntRegs;
 const int NumCCRegs = NUM_CCREGS;
 
-#define ISA_HAS_CC_REGS
-
 // Each 128 bit xmm register is broken into two effective 64 bit registers.
 // Add 8 for the indices that are mapped over the fp stack
 const int NumFloatRegs =
diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh
index 033a0777a..f25e62249 100644
--- a/src/cpu/simple_thread.hh
+++ b/src/cpu/simple_thread.hh
@@ -109,9 +109,7 @@ class SimpleThread : public ThreadState, public ThreadContext
     std::array<RegVal, TheISA::NumIntRegs> intRegs;
     std::array<VecRegContainer, TheISA::NumVecRegs> vecRegs;
     std::array<VecPredRegContainer, TheISA::NumVecPredRegs> vecPredRegs;
-#ifdef ISA_HAS_CC_REGS
     std::array<RegVal, TheISA::NumCCRegs> ccRegs;
-#endif
     TheISA::ISA *const isa;    // one "instance" of the current ISA.
 
     TheISA::PCState _pcState;
@@ -299,9 +297,7 @@ class SimpleThread : public ThreadState, public ThreadContext
             vec_reg.zero();
         for (auto &pred_reg: vecPredRegs)
             pred_reg.reset();
-#ifdef ISA_HAS_CC_REGS
         ccRegs.fill(0);
-#endif
         isa->clear();
     }
 
@@ -468,7 +464,6 @@ class SimpleThread : public ThreadState, public ThreadContext
     RegVal
     readCCReg(RegIndex reg_idx) const override
     {
-#ifdef ISA_HAS_CC_REGS
         int flatIndex = isa->flattenCCIndex(reg_idx);
         assert(0 <= flatIndex);
         assert(flatIndex < TheISA::NumCCRegs);
@@ -476,10 +471,6 @@ class SimpleThread : public ThreadState, public ThreadContext
         DPRINTF(CCRegs, "Reading CC reg %d (%d) as %#x.\n",
                 reg_idx, flatIndex, regVal);
         return regVal;
-#else
-        panic("Tried to read a CC register.");
-        return 0;
-#endif
     }
 
     void
@@ -538,15 +529,11 @@ class SimpleThread : public ThreadState, public ThreadContext
     void
     setCCReg(RegIndex reg_idx, RegVal val) override
     {
-#ifdef ISA_HAS_CC_REGS
         int flatIndex = isa->flattenCCIndex(reg_idx);
         assert(flatIndex < TheISA::NumCCRegs);
         DPRINTF(CCRegs, "Setting CC reg %d (%d) to %#x.\n",
                 reg_idx, flatIndex, val);
         setCCRegFlat(flatIndex, val);
-#else
-        panic("Tried to set a CC register.");
-#endif
     }
 
     TheISA::PCState pcState() const override { return _pcState; }
@@ -707,22 +694,8 @@ class SimpleThread : public ThreadState, public ThreadContext
         vecPredRegs[reg] = val;
     }
 
-#ifdef ISA_HAS_CC_REGS
     RegVal readCCRegFlat(RegIndex idx) const override { return ccRegs[idx]; }
     void setCCRegFlat(RegIndex idx, RegVal val) override { ccRegs[idx] = val; }
-#else
-    RegVal
-    readCCRegFlat(RegIndex idx) const override
-    {
-        panic("readCCRegFlat w/no CC regs!\n");
-    }
-
-    void
-    setCCRegFlat(RegIndex idx, RegVal val) override
-    {
-        panic("setCCRegFlat w/no CC regs!\n");
-    }
-#endif
 };
 
 
diff --git a/src/cpu/thread_context.cc b/src/cpu/thread_context.cc
index dea39015f..f8c422c98 100644
--- a/src/cpu/thread_context.cc
+++ b/src/cpu/thread_context.cc
@@ -191,12 +191,12 @@ serialize(const ThreadContext &tc, CheckpointOut &cp)
         intRegs[i] = tc.readIntRegFlat(i);
     SERIALIZE_ARRAY(intRegs, NumIntRegs);
 
-#ifdef ISA_HAS_CC_REGS
-    RegVal ccRegs[NumCCRegs];
-    for (int i = 0; i < NumCCRegs; ++i)
-        ccRegs[i] = tc.readCCRegFlat(i);
-    SERIALIZE_ARRAY(ccRegs, NumCCRegs);
-#endif
+    if (NumCCRegs) {
+        RegVal ccRegs[NumCCRegs];
+        for (int i = 0; i < NumCCRegs; ++i)
+            ccRegs[i] = tc.readCCRegFlat(i);
+        SERIALIZE_ARRAY(ccRegs, NumCCRegs);
+    }
 
     tc.pcState().serialize(cp);
 
@@ -232,12 +232,12 @@ unserialize(ThreadContext &tc, CheckpointIn &cp)
     for (int i = 0; i < NumIntRegs; ++i)
         tc.setIntRegFlat(i, intRegs[i]);
 
-#ifdef ISA_HAS_CC_REGS
-    RegVal ccRegs[NumCCRegs];
-    UNSERIALIZE_ARRAY(ccRegs, NumCCRegs);
-    for (int i = 0; i < NumCCRegs; ++i)
-        tc.setCCRegFlat(i, ccRegs[i]);
-#endif
+    if (NumCCRegs) {
+        RegVal ccRegs[NumCCRegs];
+        UNSERIALIZE_ARRAY(ccRegs, NumCCRegs);
+        for (int i = 0; i < NumCCRegs; ++i)
+            tc.setCCRegFlat(i, ccRegs[i]);
+    }
 
     PCState pcState;
     pcState.unserialize(cp);
-- 
2.30.2