From 57f373d4991057dedddb83258559764a7d7488a8 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 15 May 2020 13:58:57 +0100 Subject: [PATCH] output countzero ilang --- src/soc/countzero/test/test_countzero.py | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/src/soc/countzero/test/test_countzero.py b/src/soc/countzero/test/test_countzero.py index c6b781ad..60185196 100644 --- a/src/soc/countzero/test/test_countzero.py +++ b/src/soc/countzero/test/test_countzero.py @@ -1,5 +1,6 @@ # https://github.com/antonblanchard/microwatt/blob/master/countzero_tb.vhdl from nmigen import Module, Signal +from nmigen.cli import rtlil from nmigen.back.pysim import Simulator, Delay from nmigen.test.utils import FHDLTestCase import unittest @@ -95,5 +96,10 @@ class ZeroCounterTestCase(FHDLTestCase): if __name__ == "__main__": - unittest.main() + dut = ZeroCounter() + vl = rtlil.convert(dut, ports=dut.ports()) + with open("countzero.il", "w") as f: + f.write(vl) + + unittest.main() -- 2.30.2