From 580efecc8c6c2890ea1f3dfe147ac60646f3db53 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 7 Aug 2018 08:59:34 +0200 Subject: [PATCH] picorv32: add reset signal --- litex/soc/cores/cpu/picorv32/core.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/litex/soc/cores/cpu/picorv32/core.py b/litex/soc/cores/cpu/picorv32/core.py index ace7ee93..fb271209 100644 --- a/litex/soc/cores/cpu/picorv32/core.py +++ b/litex/soc/cores/cpu/picorv32/core.py @@ -7,6 +7,7 @@ from litex.soc.interconnect import wishbone class PicoRV32(Module): def __init__(self, platform, progaddr_reset, variant): + self.reset = Signal() self.ibus = i = wishbone.Interface() self.dbus = d = wishbone.Interface() self.interrupt = Signal(32) @@ -50,7 +51,7 @@ class PicoRV32(Module): # clock / reset i_clk=ClockSignal(), - i_resetn=~ResetSignal(), + i_resetn=~(ResetSignal() | self.reset), # trap o_trap=self.trap, -- 2.30.2