From 582b1939286fe0d552e4fbe24686863eabbb2402 Mon Sep 17 00:00:00 2001 From: lkcl Date: Fri, 21 Apr 2023 22:43:10 +0100 Subject: [PATCH] --- openpower/sv/rfc/ls001.mdwn | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/openpower/sv/rfc/ls001.mdwn b/openpower/sv/rfc/ls001.mdwn index 73a494b66..9214864b0 100644 --- a/openpower/sv/rfc/ls001.mdwn +++ b/openpower/sv/rfc/ls001.mdwn @@ -181,12 +181,12 @@ such large numbers of registers, even for Multi-Issue microarchitectures. * To hold all Vector Context, four SPRs are needed. (Some 32/32-to-64 aliases are advantageous but not critical). * Five 6-bit XO (A-Form) "Management" instructions are needed. These are - Scalar 32-bit instructions and *may* be 64-bit-extended in future - (safely within the SVP64 space: no need for an EXT001 encoding). + Scalar 32-bit instructions and *may* be 64-bit-extended in future as + EXT1xx Encodings. **Summary of Simple-V Opcode space** -* 75% of one Major Opcode (equivalent to the rest of EXT017) +* 50% of a new 64-bit Encoding (PO9) * Five 6-bit XO 32-bit "Management" operations. No further opcode space *for Simple-V* is envisaged to be required for @@ -221,6 +221,7 @@ the same space): * **svindex** - convenience instruction for setting up "Indexed" REMAP. \newpage{} + # SVP64 24-bit Prefixes The SVP64 24-bit Prefix (RM) options aim to reduce instruction count -- 2.30.2