From 582b4055ca4dc4260ab1092c6b39b3e792362c23 Mon Sep 17 00:00:00 2001 From: Jozef Lawrynowicz Date: Tue, 15 Oct 2019 12:19:51 +0000 Subject: [PATCH] msp430.md: Group zero_extend* insns together. 2019-10-15 Jozef Lawrynowicz * config/msp430/msp430.md: Group zero_extend* insns together. From-SVN: r276996 --- gcc/ChangeLog | 4 ++ gcc/config/msp430/msp430.md | 117 ++++++++++++++++++------------------ 2 files changed, 63 insertions(+), 58 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 767dc025e95..ff2c70f30bd 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,7 @@ +2019-10-15 Jozef Lawrynowicz + + * config/msp430/msp430.md: Group zero_extend* insns together. + 2019-10-15 Jozef Lawrynowicz * config/msp430/constraints.md: Allow post_inc operand for "Ya" diff --git a/gcc/config/msp430/msp430.md b/gcc/config/msp430/msp430.md index a533efa1656..2e8e8326232 100644 --- a/gcc/config/msp430/msp430.md +++ b/gcc/config/msp430/msp430.md @@ -564,15 +564,11 @@ AND%X0\t#0xff, %0" ) -;; Eliminate extraneous zero-extends mysteriously created by gcc. -(define_peephole2 - [(set (match_operand:HI 0 "register_operand") - (zero_extend:HI (match_operand:QI 1 "general_operand"))) - (set (match_operand:HI 2 "register_operand") - (zero_extend:HI (match_operand:QI 3 "register_operand")))] - "REGNO (operands[0]) == REGNO (operands[2]) && REGNO (operands[2]) == REGNO (operands[3])" - [(set (match_dup 0) - (zero_extend:HI (match_dup 1)))] +(define_insn "zero_extendqisi2" + [(set (match_operand:SI 0 "msp430_general_dst_nonv_operand" "=r") + (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "rm")))] + "" + "MOV%X1.B\t%1,%L0 { CLR\t%H0" ) (define_insn "zero_extendhipsi2" @@ -584,39 +580,6 @@ MOVX.A\t%1, %0" ) -(define_insn "truncpsihi2" - [(set (match_operand:HI 0 "msp430_general_dst_operand" "=rm") - (truncate:HI (match_operand:PSI 1 "register_operand" "r")))] - "" - "MOVX\t%1, %0" -) - -(define_insn "extendhisi2" - [(set (match_operand:SI 0 "msp430_general_dst_nonv_operand" "=r") - (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r")))] - "" - { return msp430x_extendhisi (operands); } -) - -(define_insn "extendhipsi2" - [(set (match_operand:PSI 0 "msp430_general_dst_nonv_operand" "=r") - (subreg:PSI (sign_extend:SI (match_operand:HI 1 "general_operand" "0")) 0))] - "msp430x" - "RLAM.A #4, %0 { RRAM.A #4, %0" -) - -;; Look for cases where integer/pointer conversions are suboptimal due -;; to missing patterns, despite us not having opcodes for these -;; patterns. Doing these manually allows for alternate optimization -;; paths. - -(define_insn "zero_extendqisi2" - [(set (match_operand:SI 0 "msp430_general_dst_nonv_operand" "=r") - (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "rm")))] - "" - "MOV%X1.B\t%1,%L0 { CLR\t%H0" -) - (define_insn "zero_extendhisi2" [(set (match_operand:SI 0 "msp430_general_dst_nonv_operand" "=rm,r") (zero_extend:SI (match_operand:HI 1 "general_operand" "0,r")))] @@ -635,22 +598,6 @@ MOV.W\t%1,%0" ) -(define_insn "extend_and_shift1_hipsi2" - [(set (subreg:SI (match_operand:PSI 0 "msp430_general_dst_nonv_operand" "=r") 0) - (ashift:SI (sign_extend:SI (match_operand:HI 1 "general_operand" "0")) - (const_int 1)))] - "msp430x" - "RLAM.A #4, %0 { RRAM.A #3, %0" -) - -(define_insn "extend_and_shift2_hipsi2" - [(set (subreg:SI (match_operand:PSI 0 "msp430_general_dst_nonv_operand" "=r") 0) - (ashift:SI (sign_extend:SI (match_operand:HI 1 "general_operand" "0")) - (const_int 2)))] - "msp430x" - "RLAM.A #4, %0 { RRAM.A #2, %0" -) - ; Nasty - we are sign-extending a 20-bit PSI value in one register into ; two adjacent 16-bit registers to make an SI value. There is no MSP430X ; instruction that will do this, so we push the 20-bit value onto the stack @@ -685,6 +632,60 @@ " ) + +;; Eliminate extraneous zero-extends mysteriously created by gcc. +(define_peephole2 + [(set (match_operand:HI 0 "register_operand") + (zero_extend:HI (match_operand:QI 1 "general_operand"))) + (set (match_operand:HI 2 "register_operand") + (zero_extend:HI (match_operand:QI 3 "register_operand")))] + "REGNO (operands[0]) == REGNO (operands[2]) && REGNO (operands[2]) == REGNO (operands[3])" + [(set (match_dup 0) + (zero_extend:HI (match_dup 1)))] +) + +(define_insn "truncpsihi2" + [(set (match_operand:HI 0 "msp430_general_dst_operand" "=rm") + (truncate:HI (match_operand:PSI 1 "register_operand" "r")))] + "" + "MOVX\t%1, %0" +) + +(define_insn "extendhisi2" + [(set (match_operand:SI 0 "msp430_general_dst_nonv_operand" "=r") + (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r")))] + "" + { return msp430x_extendhisi (operands); } +) + +(define_insn "extendhipsi2" + [(set (match_operand:PSI 0 "msp430_general_dst_nonv_operand" "=r") + (subreg:PSI (sign_extend:SI (match_operand:HI 1 "general_operand" "0")) 0))] + "msp430x" + "RLAM.A #4, %0 { RRAM.A #4, %0" +) + +;; Look for cases where integer/pointer conversions are suboptimal due +;; to missing patterns, despite us not having opcodes for these +;; patterns. Doing these manually allows for alternate optimization +;; paths. + +(define_insn "extend_and_shift1_hipsi2" + [(set (subreg:SI (match_operand:PSI 0 "msp430_general_dst_nonv_operand" "=r") 0) + (ashift:SI (sign_extend:SI (match_operand:HI 1 "general_operand" "0")) + (const_int 1)))] + "msp430x" + "RLAM.A #4, %0 { RRAM.A #3, %0" +) + +(define_insn "extend_and_shift2_hipsi2" + [(set (subreg:SI (match_operand:PSI 0 "msp430_general_dst_nonv_operand" "=r") 0) + (ashift:SI (sign_extend:SI (match_operand:HI 1 "general_operand" "0")) + (const_int 2)))] + "msp430x" + "RLAM.A #4, %0 { RRAM.A #2, %0" +) + ;; We also need to be able to sign-extend pointer types (eg ptrdiff_t). ;; Since (we assume) pushing a 20-bit value onto the stack zero-extends ;; it, we use a different method here. -- 2.30.2