From 58344d65ec02091a2cc5b0ba9951422189a2f0dd Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 4 Aug 2020 13:06:06 +0100
Subject: [PATCH] single-step and print out PC using DMI in litex sim

---
 src/soc/litex/florent/sim.py | 35 ++++++++++++++++++++++++++++++++++-
 1 file changed, 34 insertions(+), 1 deletion(-)

diff --git a/src/soc/litex/florent/sim.py b/src/soc/litex/florent/sim.py
index d9046f75..54db6113 100755
--- a/src/soc/litex/florent/sim.py
+++ b/src/soc/litex/florent/sim.py
@@ -51,6 +51,11 @@ class LibreSoCSim(SoCCore):
         dmi_wen = Signal(1)
         dmi_req = Signal(1)
 
+        # debug log out
+        dbg_addr = Signal(3)
+        dbg_dout = Signal(64)
+        dbg_msg = Signal(1)
+
         uptime = Signal(64)
         # increment counter, Stop after 100000 cycles
         uptime = Signal(64)
@@ -72,6 +77,19 @@ class LibreSoCSim(SoCCore):
                     )
                  ),
                 ),
+            ),
+            If(dmi_req & ~dmi_wen,
+                (self.cpu.dmi_addr.eq(dmi_addr),   # DMI Addr
+                 self.cpu.dmi_req.eq(1),    # DMI request
+                 self.cpu.dmi_wr.eq(0),    # DMI read
+                 If(self.cpu.dmi_ack,
+                    (NextState("IDLE"),
+                     NextValue(dbg_addr, dmi_addr),
+                     NextValue(dbg_dout, self.cpu.dmi_dout),
+                     NextValue(dbg_msg, 1),
+                    )
+                 ),
+                ),
             )
         )
 
@@ -84,6 +102,13 @@ class LibreSoCSim(SoCCore):
             )
         )
 
+        # debug messages out
+        self.sync += If(dbg_msg,
+             (Display("[%06x] dbg: %1x, %016x", uptime, dbg_addr, dbg_dout),
+              dbg_msg.eq(0)
+             )
+        )
+
         # kick off a "stop"
         self.sync += If(uptime == 0,
             (dmi_addr.eq(0), # CTRL
@@ -94,7 +119,7 @@ class LibreSoCSim(SoCCore):
         )
 
         # loop every 1<<N cycles
-        cyclewid = 7
+        cyclewid = 8
 
         # kick off a "step"
         self.sync += If(uptime[0:cyclewid] == 4,
@@ -105,6 +130,14 @@ class LibreSoCSim(SoCCore):
             )
         )
 
+        # get the PC
+        self.sync += If(uptime[0:cyclewid] == 8,
+            (dmi_addr.eq(0b10), # NIA
+             dmi_req.eq(1),
+             dmi_wen.eq(0),
+            )
+        )
+
         # monitor ibus write
         self.sync += If(self.cpu.ibus.stb & self.cpu.ibus.ack &
                         self.cpu.ibus.we,
-- 
2.30.2