From 5844376d53159dcbd0584c4489903d76b22fcd65 Mon Sep 17 00:00:00 2001 From: Filip Kokosinski Date: Thu, 19 Sep 2019 12:23:05 +0200 Subject: [PATCH] soc_core: adapt memory map for mainline Linux with mor1kx Mainline Linux expects it to be loaded at the physical address of 0x0. Change the MAIN_RAM base address to 0x0 and update exception vector during the booting process. --- litex/soc/integration/soc_core.py | 9 +++++++++ litex/soc/software/bios/boot.c | 9 +++++++++ 2 files changed, 18 insertions(+) diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py index 976baa4c..c2291df6 100644 --- a/litex/soc/integration/soc_core.py +++ b/litex/soc/integration/soc_core.py @@ -202,6 +202,15 @@ class SoCCore(Module): self.soc_mem_map["csr"] = 0x12000000 csr_alignment = 64 + # Mainline Linux OpenRISC arch code requires Linux kernel to be loaded + # at the physical address of 0x0. As we are running Linux from the + # MAIN_RAM region - move it to satisfy that requirement. + if cpu_type == "mor1kx" and cpu_variant == "linux": + self.soc_mem_map["main_ram"] = 0x00000000 + self.soc_mem_map["rom"] = 0x10000000 + self.soc_mem_map["sram"] = 0x50000000 + self.soc_mem_map["csr"] = 0x60000000 + if cpu_type == "None": cpu_type = None diff --git a/litex/soc/software/bios/boot.c b/litex/soc/software/bios/boot.c index 41e179f4..559c495b 100644 --- a/litex/soc/software/bios/boot.c +++ b/litex/soc/software/bios/boot.c @@ -43,6 +43,15 @@ static void __attribute__((noreturn)) boot(unsigned long r1, unsigned long r2, u #ifdef CONFIG_L2_SIZE flush_l2_cache(); #endif + +#if defined(CONFIG_CPU_TYPE_MOR1KX) && defined(CONFIG_CPU_VARIANT_LINUX) + /* Mainline Linux expects to have exception vector base address set to the + * base address of Linux kernel; it also expects to be run with an offset + * of 0x100. */ + mtspr(SPR_EVBAR, addr); + addr += 0x100; +#endif + boot_helper(r1, r2, r3, addr); while(1); } -- 2.30.2