From 5846e6bef50d185eb4d2a25f18642d78c09c613b Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 15 Dec 2021 15:49:45 +0000 Subject: [PATCH] read MSR.PR and MSR.DR and update ICache priv/virt moed during fetch --- src/soc/simple/inorder.py | 6 ++++++ src/soc/simple/issuer.py | 8 +++++++- 2 files changed, 13 insertions(+), 1 deletion(-) diff --git a/src/soc/simple/inorder.py b/src/soc/simple/inorder.py index 60676676..b6cfbcbf 100644 --- a/src/soc/simple/inorder.py +++ b/src/soc/simple/inorder.py @@ -24,6 +24,7 @@ import sys from nmutil.singlepipe import ControlBase from soc.simple.core_data import FetchOutput, FetchInput +from openpower.consts import MSR from openpower.decoder.power_enums import MicrOp from openpower.state import CoreState from soc.regfile.regfiles import StateRegs @@ -112,6 +113,11 @@ class FetchFSM(ControlBase): fetch_failed = Const(0, 1) flush_needed = False + # set priv / virt mode on I-Cache, sigh + if isinstance(self.imem, ICache): + comb += self.imem.i_in.priv_mode.eq(~msr[MSR.PR]) + comb += self.imem.i_in.virt_mode.eq(msr[MSR.DR]) + with m.FSM(name='fetch_fsm'): # waiting (zzz) diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py index 0b42aaa3..1ddb2385 100644 --- a/src/soc/simple/issuer.py +++ b/src/soc/simple/issuer.py @@ -33,7 +33,7 @@ from openpower.decoder.decode2execute1 import Data from openpower.decoder.power_enums import (MicrOp, SVP64PredInt, SVP64PredCR, SVP64PredMode) from openpower.state import CoreState -from openpower.consts import (CR, SVP64CROffs) +from openpower.consts import (CR, SVP64CROffs, MSR) from soc.experiment.testmem import TestMemory # test only for instructions from soc.regfile.regfiles import StateRegs, FastRegs from soc.simple.core import NonProductionCore @@ -688,6 +688,11 @@ class FetchFSM(ControlBase): fetch_failed = Const(0, 1) flush_needed = False + # set priv / virt mode on I-Cache, sigh + if isinstance(self.imem, ICache): + comb += self.imem.i_in.priv_mode.eq(~msr[MSR.PR]) + comb += self.imem.i_in.virt_mode.eq(msr[MSR.DR]) + with m.FSM(name='fetch_fsm'): # waiting (zzz) @@ -702,6 +707,7 @@ class FetchFSM(ControlBase): comb += self.imem.a_pc_i.eq(pc) comb += self.imem.a_i_valid.eq(1) comb += self.imem.f_i_valid.eq(1) + # transfer state to output sync += cur_state.pc.eq(pc) sync += cur_state.svstate.eq(svstate) # and svstate sync += cur_state.msr.eq(msr) # and msr -- 2.30.2