From 58494b42b58274d776c1478132809f86a7ae3e52 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Marek=20Ol=C5=A1=C3=A1k?= Date: Sun, 17 Apr 2016 16:14:32 +0200 Subject: [PATCH] radeonsi: add safety assertions for meta cache flushes MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Reviewed-by: Nicolai Hähnle --- src/gallium/drivers/radeonsi/si_state_draw.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c index 86fb4431022..c9f56c6146e 100644 --- a/src/gallium/drivers/radeonsi/si_state_draw.c +++ b/src/gallium/drivers/radeonsi/si_state_draw.c @@ -662,10 +662,14 @@ void si_emit_cache_flush(struct si_context *si_ctx, struct r600_atom *atom) if (sctx->flags & SI_CONTEXT_FLUSH_AND_INV_CB_META) { radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0) | compute); radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0)); + /* needed for wait for idle in SURFACE_SYNC */ + assert(sctx->flags & SI_CONTEXT_FLUSH_AND_INV_CB); } if (sctx->flags & SI_CONTEXT_FLUSH_AND_INV_DB_META) { radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0) | compute); radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0)); + /* needed for wait for idle in SURFACE_SYNC */ + assert(sctx->flags & SI_CONTEXT_FLUSH_AND_INV_DB); } if (sctx->flags & SI_CONTEXT_FLUSH_WITH_INV_L2) { radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0) | compute); -- 2.30.2