From 585449d4f3a78b56521ea71ddfd77f1d0515ed04 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 13 Dec 2021 12:29:06 +0000 Subject: [PATCH] TODO comments about using MSRspec --- src/soc/experiment/pimem.py | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/soc/experiment/pimem.py b/src/soc/experiment/pimem.py index 72e0834f..cb17807d 100644 --- a/src/soc/experiment/pimem.py +++ b/src/soc/experiment/pimem.py @@ -222,7 +222,12 @@ class PortInterfaceBase(Elaboratable): pi = self.pi comb += lds.eq(pi.is_ld_i) # ld-req signals comb += sts.eq(pi.is_st_i) # st-req signals + + # TODO: construct an MSRspec here and pass it over in + # self.set_rd_addr and set_wr_addr below rather than just pr pr = ~pi.priv_mode + dr = ~pi.virt_mode # not yet used + sf = self.mode_32bit # not yet used # detect busy "edge" busy_delay = Signal() -- 2.30.2