From 585b50b2922c45722a0954848080d161a4122725 Mon Sep 17 00:00:00 2001 From: Gabriel Somlo Date: Wed, 18 Dec 2019 11:24:11 -0500 Subject: [PATCH] soc_core: csr_alignment assertions Enforce the condition that csr_alignment be either 32 or 64 when requested explicitly when initializing SoCCore(). Additionally, if a CPU is specified, enforce that csr_alignment be equal to the native CPU word size (currently either 32 or 64), and warn the caller if an alignment value *higher* than the CPU native word size was explicitly requested. In conclusion, if a CPU is specified, then csr_alignment should be assumed to equal 8*sizeof(unsigned long). Signed-off-by: Gabriel Somlo --- litex/soc/integration/soc_core.py | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py index 6bafe6f1..61281f02 100644 --- a/litex/soc/integration/soc_core.py +++ b/litex/soc/integration/soc_core.py @@ -141,6 +141,8 @@ class SoCCore(Module): self.csr_data_width = csr_data_width self.csr_address_width = csr_address_width + assert csr_alignment in [32, 64] + self.with_ctrl = with_ctrl self.with_uart = with_uart @@ -200,6 +202,9 @@ class SoCCore(Module): # Allow SoCController to reset the CPU if with_ctrl: self.comb += self.cpu.reset.eq(self.ctrl.reset) + + assert csr_alignment <= self.cpu.data_width + csr_alignment = self.cpu.data_width else: self.submodules.cpu = cpu.CPUNone() self.soc_io_regions.update(self.cpu.io_regions) @@ -256,7 +261,6 @@ class SoCCore(Module): self.add_interrupt("timer0", allow_user_defined=True) # Add Wishbone to CSR bridge - csr_alignment = max(csr_alignment, self.cpu.data_width) self.config["CSR_DATA_WIDTH"] = csr_data_width self.config["CSR_ALIGNMENT"] = csr_alignment assert csr_data_width <= csr_alignment -- 2.30.2