From 58aa28fb3e8dba126747f0dbadd670ac6459f138 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 11 Jun 2020 20:03:30 +0100 Subject: [PATCH] some ugly hacks that get LD/ST immediate working --- src/soc/experiment/compldst_multi.py | 9 ++++--- src/soc/experiment/l0_cache.py | 6 +++++ src/soc/fu/ldst/test/test_pipe_caller.py | 32 +++++++++++++++++++++--- 3 files changed, 41 insertions(+), 6 deletions(-) diff --git a/src/soc/experiment/compldst_multi.py b/src/soc/experiment/compldst_multi.py index 630dc9b8..045cc12a 100644 --- a/src/soc/experiment/compldst_multi.py +++ b/src/soc/experiment/compldst_multi.py @@ -291,6 +291,9 @@ class LDSTCompUnit(RegSpecAPI, Elaboratable): comb += reset_r.eq(self.rd.go | Repl(self.go_die_i, self.n_src)) comb += reset_a.eq(self.go_ad_i | self.go_die_i) + p_st_go = Signal(reset_less=True) + sync += p_st_go.eq(self.st.go) + ########################## # FSM implemented through sequence of latches. approximately this: # - opc_l : opcode @@ -338,7 +341,7 @@ class LDSTCompUnit(RegSpecAPI, Elaboratable): # store latch comb += sto_l.s.eq(addr_ok & op_is_st) - sync += sto_l.r.eq(reset_s) + comb += sto_l.r.eq(reset_s | p_st_go) # reset latch comb += rst_l.s.eq(addr_ok) # start when address is ready @@ -428,7 +431,7 @@ class LDSTCompUnit(RegSpecAPI, Elaboratable): self.shadown_i) # provide "done" signal: select req_rel for non-LD/ST, adr_rel for LD/ST - comb += wr_any.eq(self.st.go | self.wr.go[0] | self.wr.go[1]) + comb += wr_any.eq(self.st.go | p_st_go | self.wr.go[0] | self.wr.go[1]) comb += wr_reset.eq(rst_l.q & busy_o & self.shadown_i & ~(self.st.rel | self.wr.rel[0] | self.wr.rel[1]) & (lod_l.qn | op_is_st)) @@ -461,7 +464,7 @@ class LDSTCompUnit(RegSpecAPI, Elaboratable): comb += pi.op.eq(self.oper_i) # op details (not all needed) # address comb += pi.addr.data.eq(addr_r) # EA from adder - comb += pi.addr.ok.eq(alu_ok & lod_l.q) # "go do address stuff" + comb += pi.addr.ok.eq(alu_ok & (lod_l.q | sto_l.q)) # "go do address stuff" comb += self.addr_exc_o.eq(pi.addr_exc_o) # exception occurred comb += addr_ok.eq(self.pi.addr_ok_o) # no exc, address fine # ld - ld gets latched in via lod_l diff --git a/src/soc/experiment/l0_cache.py b/src/soc/experiment/l0_cache.py index ed2823de..b6e9d6e0 100644 --- a/src/soc/experiment/l0_cache.py +++ b/src/soc/experiment/l0_cache.py @@ -455,6 +455,12 @@ class L0CacheBuffer(Elaboratable): comb += wrport.en.eq(lenexp.lexp_o) # enable writes comb += reset_l.s.eq(1) # reset mode after 1 cycle + # ugly hack, due to simultaneous addr req-go acknowledge + reset_delay = Signal(reset_less=True) + sync += reset_delay.eq(reset_l.q) + with m.If(reset_delay): + comb += adrok_l.r.eq(1) # address reset + # after waiting one cycle (reset_l is "sync" mode), reset the port with m.If(reset_l.q): comb += idx_l.s.eq(1) # deactivate port-index selector diff --git a/src/soc/fu/ldst/test/test_pipe_caller.py b/src/soc/fu/ldst/test/test_pipe_caller.py index 692fc668..3bf7ed60 100644 --- a/src/soc/fu/ldst/test/test_pipe_caller.py +++ b/src/soc/fu/ldst/test/test_pipe_caller.py @@ -77,10 +77,36 @@ class LDSTTestCase(FHDLTestCase): initial_mem=initial_mem) def test_2_load_store(self): - lst = ["stw 2, 0(1)", - "lwz 3, 0(1)"] + lst = [ + "stb 3, 1(2)", + "lbz 4, 1(2)", + ] initial_regs = [0] * 32 initial_regs[1] = 0x0004 initial_regs[2] = 0x0008 - self.run_tst_program(Program(lst), initial_regs) + initial_regs[3] = 0x00ee + initial_mem = {0x0000: (0x12345678, 8), + 0x0008: (0x54321234, 8), + 0x0010: (0x87654321, 8), + 0x0018: (0xabcdef01, 8), + 0x0040: (0x22324252, 8), + 0x0048: (0x18283848, 8)} + self.run_tst_program(Program(lst), initial_regs, + initial_mem=initial_mem) + + def test_3_load_store(self): + lst = ["sth 4, 0(2)", + "lhz 4, 0(2)"] + initial_regs = [0] * 32 + initial_regs[1] = 0x0004 + initial_regs[2] = 0x0002 + initial_regs[3] = 0x15eb + initial_mem = {0x0000: (0x12345678, 8), + 0x0008: (0x54321234, 8), + 0x0010: (0x87654321, 8), + 0x0018: (0xabcdef01, 8), + 0x0040: (0x22324252, 8), + 0x0048: (0x18283848, 8)} + self.run_tst_program(Program(lst), initial_regs, + initial_mem=initial_mem) -- 2.30.2