From 58b285da7495610032791c93faa6f7817333aa34 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 25 Nov 2021 21:38:54 +0000 Subject: [PATCH] add debug prints in old simulator --- src/soc/experiment/sim.py | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/soc/experiment/sim.py b/src/soc/experiment/sim.py index 0547bda6..d96cb54d 100644 --- a/src/soc/experiment/sim.py +++ b/src/soc/experiment/sim.py @@ -44,11 +44,13 @@ class RegSim: src2 = self.regs[src2] & maxbits if op == MicrOp.OP_ADD: val = src1 + src2 + print(" add src1, src2", src1, src2, val) elif op == MicrOp.OP_MUL_L64: val = src1 * src2 - print("mul src1, src2", src1, src2, val) + print(" mul src1, src2", src1, src2, val) elif op == ISUB: val = src1 - src2 + print(" sub src1, src2", src1, src2, val) elif op == ISHF: val = src1 >> (src2 & maxbits) elif op == IBGT: -- 2.30.2