From 58cbf20e126b5a695a8042b7a41574c4c83fec3d Mon Sep 17 00:00:00 2001 From: Doug Evans Date: Sat, 23 Mar 1996 20:54:48 +0000 Subject: [PATCH] sparc.c (arith11_operand): Use SPARC_SIMM11_P. * sparc/sparc.c (arith11_operand): Use SPARC_SIMM11_P. (arith10_operand): Use SPARC_SIMM10_P. From-SVN: r11601 --- gcc/config/sparc/sparc.c | 24 +++++++++++------------- 1 file changed, 11 insertions(+), 13 deletions(-) diff --git a/gcc/config/sparc/sparc.c b/gcc/config/sparc/sparc.c index 18284b30d5a..e6e4cccc6dd 100644 --- a/gcc/config/sparc/sparc.c +++ b/gcc/config/sparc/sparc.c @@ -709,9 +709,9 @@ cc_arithopn (op, mode) || GET_CODE (op) == IOR); } -/* Return true if OP is a register, or is a CONST_INT that can fit in a 13 - bit immediate field. This is an acceptable SImode operand for most 3 - address instructions. */ +/* Return true if OP is a register, or is a CONST_INT that can fit in a + signed 13 bit immediate field. This is an acceptable SImode operand for + most 3 address instructions. */ int arith_operand (op, mode) @@ -722,9 +722,9 @@ arith_operand (op, mode) || (GET_CODE (op) == CONST_INT && SMALL_INT (op))); } -/* Return true if OP is a register, or is a CONST_INT that can fit in an 11 - bit immediate field. This is an acceptable SImode operand for the movcc - instructions. */ +/* Return true if OP is a register, or is a CONST_INT that can fit in a + signed 11 bit immediate field. This is an acceptable SImode operand for + the movcc instructions. */ int arith11_operand (op, mode) @@ -732,13 +732,12 @@ arith11_operand (op, mode) enum machine_mode mode; { return (register_operand (op, mode) - || (GET_CODE (op) == CONST_INT - && ((unsigned) (INTVAL (op) + 0x400) < 0x800))); + || (GET_CODE (op) == CONST_INT && SPARC_SIMM11_P (INTVAL (op)))); } -/* Return true if OP is a register, or is a CONST_INT that can fit in an 10 - bit immediate field. This is an acceptable SImode operand for the movrcc - instructions. */ +/* Return true if OP is a register, or is a CONST_INT that can fit in a + signed 10 bit immediate field. This is an acceptable SImode operand for + the movrcc instructions. */ int arith10_operand (op, mode) @@ -746,8 +745,7 @@ arith10_operand (op, mode) enum machine_mode mode; { return (register_operand (op, mode) - || (GET_CODE (op) == CONST_INT - && ((unsigned) (INTVAL (op) + 0x200) < 0x400))); + || (GET_CODE (op) == CONST_INT && SPARC_SIMM10_P (INTVAL (op)))); } /* Return true if OP is a register, is a CONST_INT that fits in a 13 bit -- 2.30.2