From 58dac2fa3980bc0d882ea84db96607fd7f5d43e6 Mon Sep 17 00:00:00 2001 From: lkcl Date: Mon, 5 Aug 2019 06:09:12 +0100 Subject: [PATCH] --- simple_v_extension/sv_prefix_proposal.rst | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/simple_v_extension/sv_prefix_proposal.rst b/simple_v_extension/sv_prefix_proposal.rst index d49b8d1f9..a640e10c4 100644 --- a/simple_v_extension/sv_prefix_proposal.rst +++ b/simple_v_extension/sv_prefix_proposal.rst @@ -90,12 +90,11 @@ base FP instructions by using 10 (H) in the floating-point format field Compressed Instructions ======================= -This proposal does not include any prefixed RVC instructions, instead, -it will include 32-bit instructions that are compressed forms of -SVprefix 48-bit instructions, in the same manner that RVC instructions -are compressed forms of RVI instructions. The compressed instructions -will be defined later by considering which 48-bit instructions are the -most common. +Compressed instructions are under evaluation by taking the same +prefix as used in P48, embedding that and standard RVC opcodes (minus +their RVC prefix) into a 32-bit space. This by taking the three remaining +Major "custom" opcodes (0-2), one for each of the three RVC Quadrants. +see [[discussion]]. 48-bit Prefixed Instructions ============================ -- 2.30.2