From 58dd493b1898fbbd3ae089e8e7665ff83c1ebd89 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 27 Apr 2021 19:46:57 +0100 Subject: [PATCH] add option to enable/disable bus forwarding mode on INT regfile --- src/soc/regfile/regfile.py | 5 +++-- src/soc/regfile/regfiles.py | 2 +- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/src/soc/regfile/regfile.py b/src/soc/regfile/regfile.py index 30063726..710fc268 100644 --- a/src/soc/regfile/regfile.py +++ b/src/soc/regfile/regfile.py @@ -107,11 +107,12 @@ class RegFileArray(Elaboratable): and read-en signals (per port). """ - def __init__(self, width, depth, synced=True): + def __init__(self, width, depth, synced=True, fwd_bus_mode=True): self.synced = synced self.width = width self.depth = depth - self.regs = Array(Register(width, synced=synced) \ + self.regs = Array(Register(width, synced=synced, + writethru=fwd_bus_mode) \ for _ in range(self.depth)) self._rdports = [] self._wrports = [] diff --git a/src/soc/regfile/regfiles.py b/src/soc/regfile/regfiles.py index 030a8d28..8ac0b123 100644 --- a/src/soc/regfile/regfiles.py +++ b/src/soc/regfile/regfiles.py @@ -70,7 +70,7 @@ class IntRegs(RegFileMem): #class IntRegs(RegFileArray): * write-through capability (read on same cycle as write) """ def __init__(self, svp64_en=False, regreduce_en=False): - super().__init__(64, 32) + super().__init__(64, 32, fwd_bus_mode=not regreduce_en) self.w_ports = {'o': self.write_port("dest1"), } self.r_ports = { -- 2.30.2