From 592379169451ebddaffe59716dda097e448e7823 Mon Sep 17 00:00:00 2001 From: lkcl Date: Tue, 12 Apr 2022 04:04:08 +0100 Subject: [PATCH] --- openpower/sv/cr_ops.mdwn | 17 +++++++---------- 1 file changed, 7 insertions(+), 10 deletions(-) diff --git a/openpower/sv/cr_ops.mdwn b/openpower/sv/cr_ops.mdwn index f8a7a4a18..f224e0902 100644 --- a/openpower/sv/cr_ops.mdwn +++ b/openpower/sv/cr_ops.mdwn @@ -71,16 +71,13 @@ SVP64 RM `MODE` (includes `ELWIDTH` bits) for CR-based operations: | 4 | 5 | 19-20 | 21 | 22 23 | description | | - | - | ----- | --- |---------|----------------- | -|sz |SNZ| 00 | 0 | dz / | normal mode | -|sz |SNZ| 00 | 1 | 0 RG | scalar reduce mode (mapreduce), SUBVL=1 | -|sz |SNZ| 00 | 1 | 1 / | parallel reduce mode (mapreduce), SUBVL=1 | -|sz |SNZ| 00 | 1 | SVM RG | subvector reduce mode, SUBVL>1 | -|sz |SNZ| 01/10 | inv | CR-bit | Ffirst 3-bit mode | -|sz |SNZ| 01/10 | inv | dz / | Ffirst 5-bit mode | -|sz |SNZ| 11 | rsv | rsvd | reserved | - -`VLI=0` when bits 19-20=0b01. -`VLI=1` when bits 19-20=0b10. +|sz |SNZ| 0 0 | 0 | dz / | normal mode | +|sz |SNZ| 0 0 | 1 | 0 RG | scalar reduce mode (mapreduce), SUBVL=1 | +|sz |SNZ| 0 0 | 1 | 1 / | parallel reduce mode (mapreduce), SUBVL=1 | +|sz |SNZ| 0 0 | 1 | SVM RG | subvector reduce mode, SUBVL>1 | +|sz |SNZ| 0 1 | rsv | rsvd | reserved | +|sz |SNZ| 1 VLI | inv | CR-bit | Ffirst 3-bit mode | +|sz |SNZ| 1 VLI | inv | dz / | Ffirst 5-bit mode | Fields: -- 2.30.2