From 592a3e40379710bae41ccd3cb4ac96cabbeeb467 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 10 Apr 2023 11:22:38 +0100 Subject: [PATCH] whoops heading1 not heading2 --- openpower/sv/rfc/ls012.mdwn | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openpower/sv/rfc/ls012.mdwn b/openpower/sv/rfc/ls012.mdwn index 77df72492..475d4b3b2 100644 --- a/openpower/sv/rfc/ls012.mdwn +++ b/openpower/sv/rfc/ls012.mdwn @@ -316,7 +316,7 @@ introduce mv Swizzle operations, which can always be Macro-op fused in exactly the same way that ARM SVE predicated-move extends 3-operand "overwrite" opcodes to full independent 3-in 1-out. -# BMI (bitmanipulation) group. +## BMI (bitmanipulation) group. Whilst the [[sv/vector_ops]] instructions are only two in number, in reality the `bmask` instruction has a Mode field allowing it to cover -- 2.30.2