From 592d8c0a5d193d3aad03437942a54a667477acea Mon Sep 17 00:00:00 2001 From: Jim Wilson Date: Thu, 3 Jan 2019 11:12:17 -0800 Subject: [PATCH] RISC-V: Fix wrong use of s0 register name. s0 is listed as both an int register name and an FP register name. The FP reg name is wrong. This looks like a simple editting error, and has an easy fix. Tested with riscv64-linux build and check, with no regressions. gdb/ * riscv-tdep.c (riscv_freg_feature): Drop s0 name from f8. --- gdb/ChangeLog | 4 ++++ gdb/riscv-tdep.c | 2 +- 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/gdb/ChangeLog b/gdb/ChangeLog index 92ba43d7af9..7d5fc4597de 100644 --- a/gdb/ChangeLog +++ b/gdb/ChangeLog @@ -1,3 +1,7 @@ +2019-01-03 Jim Wilson + + * riscv-tdep.c (riscv_freg_feature): Drop s0 name from f8. + 2019-01-02 Tom Tromey * xml-tdesc.c (xml_cache): Hold a target_desc_up. diff --git a/gdb/riscv-tdep.c b/gdb/riscv-tdep.c index 33c1c4408ec..7a21efc60ef 100644 --- a/gdb/riscv-tdep.c +++ b/gdb/riscv-tdep.c @@ -185,7 +185,7 @@ static const struct riscv_register_feature riscv_freg_feature = { RISCV_FIRST_FP_REGNUM + 5, { "ft5", "f5" }, true }, { RISCV_FIRST_FP_REGNUM + 6, { "ft6", "f6" }, true }, { RISCV_FIRST_FP_REGNUM + 7, { "ft7", "f7" }, true }, - { RISCV_FIRST_FP_REGNUM + 8, { "fs0", "f8", "s0" }, true }, + { RISCV_FIRST_FP_REGNUM + 8, { "fs0", "f8" }, true }, { RISCV_FIRST_FP_REGNUM + 9, { "fs1", "f9" }, true }, { RISCV_FIRST_FP_REGNUM + 10, { "fa0", "f10" }, true }, { RISCV_FIRST_FP_REGNUM + 11, { "fa1", "f11" }, true }, -- 2.30.2