From 5931c6eda17ab5e819139046a59be28b1d766435 Mon Sep 17 00:00:00 2001 From: Andrey Miroshnikov Date: Sat, 22 Jan 2022 21:51:37 +0000 Subject: [PATCH] Fixed embedded images --- docs/pinmux.mdwn | 4 ++-- docs/pinmux/temp_pinmux_info.mdwn | 6 +++--- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/docs/pinmux.mdwn b/docs/pinmux.mdwn index 018a41fa2..4a91b7554 100644 --- a/docs/pinmux.mdwn +++ b/docs/pinmux.mdwn @@ -413,11 +413,11 @@ there will be a lag on the output data compared to the incoming [[!img gpio_block.png]] -[[!img io_mux_bank_planning.JPG]] +[[!img io_mux_bank_planning.JPG size="600px"]] # Core/Pad Connection + JTAG Mux Diagram constructed from the nmigen plat.py file. -[[!img i_o_io_tristate_jtag.JPG]] +[[!img i_o_io_tristate_jtag.JPG size="600x"]] diff --git a/docs/pinmux/temp_pinmux_info.mdwn b/docs/pinmux/temp_pinmux_info.mdwn index 2f417b35d..596c5ec2c 100644 --- a/docs/pinmux/temp_pinmux_info.mdwn +++ b/docs/pinmux/temp_pinmux_info.mdwn @@ -134,7 +134,7 @@ the signals are correct. # Pinmux GPIO Block ## Diagram -[[!img banked_gpio_block.png size="600x"]] +[[!img banked_gpio_block.jpg size="600x"]] ## Explanation The simple GPIO module is multi-GPIO block integral to the pinmux system. @@ -181,7 +181,7 @@ state of the configuration as part of the code (essentially a shadow register). The diagram below shows the layout of the configuration byte, and how it fits within a 64-bit data word. -[[!img gpio_csr_example.png size="600x"]] +[[!img gpio_csr_example.jpg size="600x"]] If the block is created with more GPIOs than can fit in a single data word, the next set of GPIOs can be accessed by incrementing the address. @@ -190,7 +190,7 @@ For example, if 16 GPIOs are instantiated and 64-bit data bus is used, GPIOs (TODO: DOES ADDRESS COUNT WORDS OR BYTES?) ## Example Memory Map -[[!img gpio_memory_example.png size="600x"]] +[[!img gpio_memory_example.jpg size="600x"]] The diagrams above show the difference in memory layout between 16-GPIO block implemented with 64-bit and 32-bit WB data buses. The 64-bit case shows there are two rows with eight GPIOs in each, and it will take two writes (assuming simple WB write) to completely configure all 16 GPIOs. The 32-bit on the other hand has four address rows, and so will take four write transactions. -- 2.30.2