From 594eaafbcc627f821d38f160921d33422a42305d Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 3 Aug 2018 09:32:00 +0100 Subject: [PATCH] pep8 cleanup --- src/bsv/actual_pinmux.py | 3 +++ src/bsv/interface_decl.py | 7 ++++--- src/bsv/peripheral_gen/base.py | 25 ++++++++++++------------- src/bsv/peripheral_gen/flexbus.py | 4 ++-- src/bsv/peripheral_gen/gpio.py | 4 ++-- src/bsv/peripheral_gen/sdram.py | 8 ++++---- src/bsv/peripheral_gen/uart.py | 2 +- src/bsv/pinmux_generator.py | 11 ++++++++++- src/ifacebase.py | 5 ++++- src/parse.py | 10 +++++----- src/spec/i_class.py | 6 +++--- src/spec/microtest.py | 14 +++++++------- 12 files changed, 57 insertions(+), 42 deletions(-) diff --git a/src/bsv/actual_pinmux.py b/src/bsv/actual_pinmux.py index e7f83e3..1d1fcd4 100644 --- a/src/bsv/actual_pinmux.py +++ b/src/bsv/actual_pinmux.py @@ -204,6 +204,7 @@ def init(p, ifaces): #print cell, temp, x dedcell(p, x, cell) + def muxcell(p, cname, x, cell, i): if x == "input": p.pinmux += \ @@ -212,6 +213,8 @@ def muxcell(p, cname, x, cell, i): p.pinmux += \ mux_wire.format(cell[0], i, "wr" + cname + "_in") + "\n" + + def dedcell(p, x, cell): if x == "input": p.pinmux += \ diff --git a/src/bsv/interface_decl.py b/src/bsv/interface_decl.py index b6517e4..afc7be9 100644 --- a/src/bsv/interface_decl.py +++ b/src/bsv/interface_decl.py @@ -510,8 +510,8 @@ class InterfaceMultiBus(object): b = InterfaceBus(buspins, is_inout, namelist, bitspec, filterbus) print "add bus", is_inout, namelist, filterbus, \ - map(lambda x:x.name_, buspins), \ - map(lambda x:x.name_, nbuspins) + map(lambda x: x.name_, buspins), \ + map(lambda x: x.name_, nbuspins) self.multibus_specs.append(b) self.multibus_specs[0].pins_ = nbuspins self.multibus_specs[0].nonbuspins = nbuspins @@ -582,11 +582,12 @@ class InterfaceSD(InterfaceMultiBus, Interface): Interface.__init__(self, ifacename, pinspecs, ganged, single) InterfaceMultiBus.__init__(self, self.pins) self.add_bus(True, ['out', 'out_en', 'in'], - "Bit#({0})", "d") + "Bit#({0})", "d") def ifacedef2(self, *args): return InterfaceMultiBus.ifacedef2(self, *args) + class InterfaceNSPI(InterfaceBus, Interface): def __init__(self, *args): diff --git a/src/bsv/peripheral_gen/base.py b/src/bsv/peripheral_gen/base.py index ed9fe4f..35d4d7c 100644 --- a/src/bsv/peripheral_gen/base.py +++ b/src/bsv/peripheral_gen/base.py @@ -80,7 +80,8 @@ class PBase(object): res = [] for cfg in self.peripheral.configs: res.append(cfg.get('mmap', None)) - return res[0] # XXX HACK! assume all configs same for each peripheral! + # XXX HACK! assume all configs same for each peripheral! + return res[0] def get_mmap_cfg_name(self, idx): cfg = self.get_mmap_configs() @@ -89,7 +90,7 @@ class PBase(object): if isinstance(nregs, int) or len(nregs) == 1: return "" return "_%d_" % idx - return cfg[idx][0] + return cfg[idx][0] def num_axi_regs32cfg(self): cfg = self.get_mmap_configs() @@ -169,7 +170,7 @@ class PBase(object): for (i, nregs) in enumerate(offs): cfg = self.get_mmap_cfg_name(i) name_ = self.axi_slave_name(cfg, name, ifacenum, typ) - res.append("typedef {0} {1};".format(idx+i, name_)) + res.append("typedef {0} {1};".format(idx + i, name_)) return ('\n'.join(res), len(offs)) def axi_fastaddr_map(self, name, ifacenum): @@ -228,7 +229,7 @@ else""" else: ps_ = ps cn = self._mk_actual_connection('out', name, - count, typ, + count, typ, pname, ps_, n_, fname) ret += cn fname = None @@ -239,7 +240,7 @@ else""" fname = "{0}.{1}".format(n_, fname) fname = self.pinname_tweak(pname, 'outen', fname) cn = self._mk_actual_connection('outen', name, - count, typ, + count, typ, pname, ps, n, fname) ret += cn if typ == 'in' or typ == 'inout': @@ -298,17 +299,16 @@ else""" elif ctype == 'in': if ck == PBase.get_clock_reset(self, name, count): ret.append("mkConnection({1},\n\t\t\t{0});".format( - ps, n)) + ps, n)) else: n2 = "{0}{1}".format(name, count) sync = '{0}_{1}_sync'.format(n2, pname) ret.append("mkConnection({1}.put,\n\t\t\t{0});".format( - ps, sync)) + ps, sync)) ret.append("mkConnection({1},\n\t\t\t{0}.get);".format( - sync, n)) + sync, n)) return ret - def _mk_clk_con(self, name, count, ctype): ret = [] ck = self.get_clock_reset(name, count) @@ -325,7 +325,7 @@ Ifc_sync#({0}) {1}_sync <-mksyncconnection( for p in self.peripheral.pinspecs: typ = p['type'] pname = p['name'] - n = name + n = name if typ == 'out' or typ == 'inout': fname = self.pinname_out(pname) if not fname: @@ -370,8 +370,7 @@ Ifc_sync#({0}) {1}_sync <-mksyncconnection( n_ = '{0}_{1}'.format(n_, pname) if typ == 'in' or typ == 'inout': ck, spc = spc, ck - return template.format(bitspec, n_, ck, spc) - + return template.format(bitspec, n_, ck, spc) def mk_cellconn(self, *args): return '' @@ -398,7 +397,7 @@ Ifc_sync#({0}) {1}_sync <-mksyncconnection( def __mk_master_connection(self, con, aname, count, fabricname): txt = "mkConnection ({0}, {2}.v_from_masters\n" + \ - " [fromInteger(valueOf({1}))]);\n" + " [fromInteger(valueOf({1}))]);\n" print "PBase __mk_master_connection", self.name, aname if not con: diff --git a/src/bsv/peripheral_gen/flexbus.py b/src/bsv/peripheral_gen/flexbus.py index 3d71cdb..4725496 100644 --- a/src/bsv/peripheral_gen/flexbus.py +++ b/src/bsv/peripheral_gen/flexbus.py @@ -11,7 +11,7 @@ class flexbus(PBase): def extfastifinstance(self, name, count): return "// TODO" + self._extifinstance(name, count, "_out", "", True, - ".flexbus_side") + ".flexbus_side") def fastifdecl(self, name, count): return "//interface FlexBus_Master_IFC fb{0}_out;".format(count) @@ -55,7 +55,7 @@ class flexbus(PBase): def _mk_pincon(self, name, count, typ): ret = [PBase._mk_pincon(self, name, count, typ)] - assert typ == 'fast' # TODO slow? + assert typ == 'fast' # TODO slow? for pname, stype, ptype in [ ('cs', 'm_FBCSn', 'out'), ('bwe', 'm_BWEn', 'out'), diff --git a/src/bsv/peripheral_gen/gpio.py b/src/bsv/peripheral_gen/gpio.py index c01dd1a..d67ab8f 100644 --- a/src/bsv/peripheral_gen/gpio.py +++ b/src/bsv/peripheral_gen/gpio.py @@ -38,9 +38,9 @@ class gpio(PBase): print "gpioslow", self.peripheral, dir(self.peripheral) print "gpioslow", self.peripheral.configs size = len(self.peripheral.pinspecs) - dflt_ = "%s" % ("0"*size*2) # default if not set in spec + dflt_ = "%s" % ("0" * size * 2) # default if not set in spec dflt = self.peripheral.configs[0].get("muxconfig", dflt_) - return "MUX#(%d) mux{0} <- mkmux('b%s);\n" % (size, dflt)+ \ + return "MUX#(%d) mux{0} <- mkmux('b%s);\n" % (size, dflt) + \ "GPIO#(%d) gpio{0} <- mkgpio();" % size def mk_connection(self, count, fabricname, typ): diff --git a/src/bsv/peripheral_gen/sdram.py b/src/bsv/peripheral_gen/sdram.py index afc6908..b1ab724 100644 --- a/src/bsv/peripheral_gen/sdram.py +++ b/src/bsv/peripheral_gen/sdram.py @@ -12,11 +12,11 @@ class sdram(PBase): def extfastifinstance(self, name, count): return "// TODO" + self._extifinstance(name, count, "_out", "", True, - ".if_sdram_out") + ".if_sdram_out") def fastifdecl(self, name, count): return "// (*always_ready*) interface " + \ - "Ifc_sdram_out sdr{0}_out;".format(count) + "Ifc_sdram_out sdr{0}_out;".format(count) def get_clk_spc(self, typ): return "clk0, rst0" @@ -30,7 +30,7 @@ class sdram(PBase): def _mk_connection(self, name=None, count=0): return ["sdr{0}.axi4_slave_sdram", "sdr{0}.axi4_slave_cntrl_reg"] - + def pinname_out(self, pname): return {'sdrwen': 'ifc_sdram_out.osdr_we_n', 'sdrcsn0': 'ifc_sdram_out.osdr_cs_n', @@ -57,7 +57,7 @@ class sdram(PBase): def _mk_pincon(self, name, count, typ): ret = [PBase._mk_pincon(self, name, count, typ)] - assert typ == 'fast' # TODO slow? + assert typ == 'fast' # TODO slow? for pname, stype, ptype in [ ('dqm', 'osdr_dqm', 'out'), ('ba', 'osdr_ba', 'out'), diff --git a/src/bsv/peripheral_gen/uart.py b/src/bsv/peripheral_gen/uart.py index 430d798..953ed12 100644 --- a/src/bsv/peripheral_gen/uart.py +++ b/src/bsv/peripheral_gen/uart.py @@ -15,7 +15,7 @@ class uart(PBase): return 8 def get_clock_reset(self, name, count): - return "uart_clock,uart_reset" + return "uart_clock,uart_reset" def mkslow_peripheral(self, size=0): return "Ifc_Uart_bs uart{0} <- \n" + \ diff --git a/src/bsv/pinmux_generator.py b/src/bsv/pinmux_generator.py index 5ccaa34..a20fc7d 100644 --- a/src/bsv/pinmux_generator.py +++ b/src/bsv/pinmux_generator.py @@ -111,7 +111,16 @@ def pinmuxgen(pth=None, verify=True): write_soc(soc, soct, fastmf, fastmt, fastid, fastit, p, ifaces, iocells) -def write_slow(slow, slowt, slowmf, slowmt, slowid, slowit, p, ifaces, iocells): +def write_slow( + slow, + slowt, + slowmf, + slowmt, + slowid, + slowit, + p, + ifaces, + iocells): """ write out the slow_peripherals.bsv file. joins all the peripherals together into one AXI Lite interface """ diff --git a/src/ifacebase.py b/src/ifacebase.py index beafc4e..fb5cd7a 100644 --- a/src/ifacebase.py +++ b/src/ifacebase.py @@ -6,6 +6,7 @@ try: except ImportError: from collections import UserDict + def _decode_list(data): rv = [] for item in data: @@ -18,6 +19,7 @@ def _decode_list(data): rv.append(item) return rv + def _decode_dict(data): rv = {} for key, value in data.iteritems(): @@ -32,6 +34,7 @@ def _decode_dict(data): rv[key] = value return rv + class InterfacesBase(UserDict): """ contains a list of interface definitions """ @@ -105,7 +108,7 @@ class InterfacesBase(UserDict): name = "%s%d" % (fname, i) cfgs.append(self.configs.get(name, {})) return cfgs - + def getifacetype(self, fname): # finds the interface type, e.g sd_d0 returns "inout" for iface in self.values(): diff --git a/src/parse.py b/src/parse.py index b2e017a..8d67b01 100644 --- a/src/parse.py +++ b/src/parse.py @@ -26,7 +26,7 @@ class Parse(object): self.muxed_cells_bank = [] self.dedicated_cells = [] self.pinnumbers = [] - self.bankwidths = {} + self.bankwidths = {} self.banksize = {} self.bankstart = {} @@ -39,7 +39,7 @@ class Parse(object): self.bankwidths[line1[0]] = int(line1[3]) self.banksize[line1[0]] = int(line1[2]) self.bankstart[line1[0]] = int(line1[1]) - + # == capture the number of IO cells required == # fname = 'pinmap.txt' if pth: @@ -53,9 +53,9 @@ class Parse(object): self.muxed_cells_bank.append(line1[1]) self.muxed_cells_width.append(int(line1[2])) # XXX TODO: dedicated pins in separate file - #if len(line1) == 2: # dedicated + # if len(line1) == 2: # dedicated # self.dedicated_cells.append(line1) - #else: + # else: for i in range(3, len(line1)): # XXX HORRIBLE HACK!! if line1[i].startswith('pwm'): @@ -77,7 +77,7 @@ class Parse(object): #print("Muxer bit width: " + str(self.cell_bitwidth)) print("Muxed IOs: " + str(len(self.muxed_cells))) print("Dedicated IOs: " + str(len(self.dedicated_cells))) - #sys.exit(0) + # sys.exit(0) def do_checks(self): """ Multiple checks to see if the user has not screwed up diff --git a/src/spec/i_class.py b/src/spec/i_class.py index e33c1fa..9f890f3 100644 --- a/src/spec/i_class.py +++ b/src/spec/i_class.py @@ -63,14 +63,14 @@ def pinspec(): ps = PinSpec(pinbanks, fixedpins, function_names, {'lcd': {'bus': 'fastbus', 'mmap': [['Cfg', 0x20000, 10] - ]}, + ]}, 'jtag': {'bus': 'fastbus'}, 'fb': {'bus': 'fastbus'}, 'sdr': {'bus': 'fastbus', 'mmap': [['Mem', 0x50000000, 0x400000], ['Cfg', 0x21000, 12] - ]}, - }) + ]}, + }) # Bank A, 0-27 ps.gpio("", ('A', 0), 0, 0, 28) diff --git a/src/spec/microtest.py b/src/spec/microtest.py index 2a8e663..9508b08 100644 --- a/src/spec/microtest.py +++ b/src/spec/microtest.py @@ -8,7 +8,7 @@ from spec.ifaceprint import display_fixed def pinspec(): pinbanks = { - 'A': (3, 4), + 'A': (3, 4), } fixedpins = { 'CTRL_SYS': [ @@ -48,12 +48,12 @@ def pinspec(): } ps = PinSpec(pinbanks, fixedpins, function_names, - { "gpioa" : - { - "muxconfig" : "011000" - } - } - ) + {"gpioa": + { + "muxconfig": "011000" + } + } + ) # Bank A, 0-3 ps.gpio("", ('A', 0), 0, 0, 3) -- 2.30.2